Datasheet

Intel
®
High Definition Audio
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Intel
®
Atom™ Processor E6xx Series Datasheet
137
9.0 Intel
®
High Definition Audio
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9.1 Overview
The Intel
®
High Definition Audio
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controller consists of a set of DMA engines that are
used to move samples of digitally encoded data between system memory and an
external codec(s). The controller communicates with the external codec(s) over the
Intel
®
HD Audio
β
serial link. The Intel
®
Atom™ Processor E6xx Series implements two
output DMA engines and two input DMA engines. The Output DMA engines move digital
data from system memory to a D-A converter in a codec. The processor implements a
single Serial Data Output signal (HDA_SDO) that is connected to all external codecs.
The Input DMA engines move digital data from the A-D converter in the codec to
system memory. The processor supports up to two external codecs by implementing
two Serial Data Input signals (HDA_SDI[1:0]), one dedicated to each of the supported
codecs.
Audio software renders outbound, and processes inbound data to/from buffers in
system memory. The location of the individual buffers is described by a Buffer
Descriptor List (BDL) that is fetched and processed by the controller. The data in the
buffers is arranged in a pre-defined format. The output DMA engines fetch the digital
data from memory and reformat it based on the programmed sample rate, bits/sample
and number of channels. The data from the output DMA engines is then combined and
serially sent to the external codec(s) over the Intel
®
HD Audio
β
link. The Input DMA
engines receive data from the codec(s) over the Intel
®
HD Audio
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link and format the
data based on the programmable attributes for that stream. The data is then written to
memory in the pre-defined format for software to process. Each DMA engine moves
one “stream” of data. A single codec can accept or generate multiple “streams” of data,
one for each A-D or D-A converter in the codec. Multiple codecs can accept the same
output “stream” processed by a single DMA engine.
Codec commands and responses are also transported to and from the codec via DMA
engines. The DMA engine dedicated to transporting commands from the Command
Output Ring Buffer (CORB) in memory to the codec(s) is called the CORB engine. The
DMA engine dedicated to transporting responses from the codec(s) to the Response
Input Ring Buffer in memory is called the RIRB engine. Every command sent to a codec
yields a response from that codec. Some commands are “broadcast” type commands in
which case a response will be generated from each codec. A codec may also be
programmed to generate unsolicited responses, which the RIRB engine also processes.
The processor also supports Programmed IO-based Immediate Command/Response
transport mechanism that can be used by BIOS for memory initialization.
9.2 Docking
The processor controls an external switch that is used to either electrically connect or
isolate a dock codec in the docking station from the processor and the Intel
®
HD Audio
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codec(s) on the motherboard. Prior to and during the physical docking process the dock
codec will be electrically isolated from the processor’s Intel
®
HD Audio
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interface. When
the physical docking occurs, software will be notified via ACPI control methods.
Software then initiates the docking sequence in the Intel
®
HD Audio
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controller. The
Intel
®
HD Audio
β
controller manages the external switch such that the electrical
connection between the dock codec and the processor’s Intel
®
HD Audio
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interface
occurs during the proper time within the frame sequence and when the signals are not
transitioning.
The processor also drives a dedicated reset signal to the dock codec(s). It sequences
the switch control signal and dedicated reset signal correctly such that the dock codec
experiences a “normal” reset as specified in the Intel
®
HD Audio
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specification.