Datasheet

Graphics, Video, and Display
Intel
®
Atom™ Processor E6xx Series Datasheet
101
00b RW
SMI_OR_SCI_E
VENT
MCE: If MCS=1, setting this bit causes an SCI. If MCS=0, setting this bit
causes an SMI. A 1 to 0, 0 to 0 or 1 to 1 transition of this bit does not
trigger any events. The graphics driver writes to this register as a means
to interrupt the SBIOS.
Table 100. E4h: GVD.ASLE – System Display Event Register
Size: 32 bit Default: 00000000h Power Well: Core
Access
PCI Configuration B:D:F 0:2:0
Offset Start:
Offset End:
E4h
Message Bus Port:
06h
Register Address: 39h
Bit Range Default Access Acronym Description
31 :24 00h RW
ASLE_SCRATCH
_TRIGGER_3
AST3: The writing of this by field (byte) - even if just writing back the
original contents - will trigger a display controller interrupt (when the
memory interface register bits IER[0] = 1 and IMR[0] = 0). If written as
part of a 16-bit or 32-bit write, only one interrupt is generated in
common.
23 :16 00h RW
ASLE_SCRATCH
_TRIGGER_2
AST2: The writing of this by field (byte) - even if just writing back the
original contents - will trigger a display controller interrupt (when the
memory interface register bits IER[0] = 1 and IMR[0] = 0). If written as
part of a 16-bit or 32-bit write, only one interrupt is generated in
common.
15 :8 00h RW
ASLE_SCRATCH
_TRIGGER_1
AST1: The writing of this by field (byte) - even if just writing back the
original contents - will trigger a display controller interrupt (when the
memory interface register bits IER[0] = 1 and IMR[0] = 0). If written as
part of a 16-bit or 32-bit write, only one interrupt is generated in
common.
7 :0 00h RW
ASLE_SCRATCH
_TRIGGER_0
AST0: The writing of this by field (byte) - even if just writing back the
original contents - will trigger a display controller interrupt (when the
memory interface register bits IER[0] = 1 and IMR[0] = 0). If written as
part of a 16-bit or 32-bit write, only one interrupt is generated in
common.
Table 101. F4h: GVD.LBB – Legacy Backlight Brightness (Sheet 1 of 2)
Size: 32 bit Default: 00000000h Power Well: Core
Access
PCI Configuration B:D:F 0:2:0
Offset Start:
Offset End:
F4h
Message Bus Port:
06h
Register Address: 39h
Bit Range Default Access Acronym Description
31 :24 00h RW SCRATCH_3
Software scratch byte 3. Any write to this byte, even writing back the
same value read, will trigger GVD to send the contents of
LEGACY_BACKLIGHT_BRIGHTNESS byte to the VSunit.
Table 99. E0h: GVD.SWSMISCI – Software SMI or SCI (Sheet 2 of 2)
Size: 32 bit Default: 00000000h Power Well: Core
Access
PCI Configuration B:D:F 0:2:0
Offset Start:
Offset End:
E0h
Message Bus Port:
06h
Register Address: 38h
Bit Range Default Access Acronym Description