Datasheet

Signal Description
90 Datasheet, Volume 1
6.7 Direct Media Interface (DMI) Signals
6.8 Phase Lock Loop (PLL) Signals
6.9 Test Access Points (TAP) Signals
FDI1_TX[3:0]
FD1I_TX#[3:0]
Intel
®
Flexible Display Interface Transmit Differential
Pair: Pipe B and C
O
FDI
FDI1_FSYNC[1]
Intel
®
Flexible Display Interface Frame Sync: Pipe B and C I
CMOS
FDI1_LSYNC[1]
Intel
®
Flexible Display Interface Line Sync: Pipe B and C I
CMOS
FDI_INT
Intel
®
Flexible Display Interface Hot-Plug Interrupt I
Asynchronous
CMOS
Table 6-9. Direct Media Interface (DMI) Signals – Processor to PCH Serial Interface
Signal Name Description
Direction/
Buffer Type
DMI_RX[3:0]
DMI_RX#[3:0]
DMI Input from PCH: Direct Media Interface receive
differential pair.
I
DMI
DMI_TX[3:0]
DMI_TX#[3:0]
DMI Output to PCH: Direct Media Interface transmit
differential pair.
O
DMI
Table 6-10. Phase Lock Loop (PLL) Signals
Signal Name Description
Direction/
Buffer Type
BCLK
BCLK#
Differential bus clock input to the processor I
Diff Clk
DPLL_REF_CLK
DPLL_REF_CLK#
Embedded Display Port PLL Differential Clock In: 120 MHz. I
Diff Clk
Table 6-11. Test Access Points (TAP) Signals (Sheet 1 of 2)
Signal Name Description
Direction/
Buffer Type
BPM#[7:0]
Breakpoint and Performance Monitor Signals: These signals
are outputs from the processor that indicate the status of
breakpoints and programmable counters used for monitoring
processor performance.
I/O
CMOS
BCLK_ITP
BCLK_ITP#
These signals are connected in parallel to the top side debug
probe to enable debug capacities.
I
DBR#
DBR# is used only in systems where no debug port is
implemented on the system board. DBR# is used by a debug
port interposer so that an in-target probe can drive system
reset.
O
Table 6-8. Intel
®
Flexible Display (Intel
®
FDI) Interface (Sheet 2 of 2)
Signal Name Description
Direction/
Buffer Type