Datasheet

8 Datasheet, Volume 1
4-10 P_LVLx to MWAIT Conversion .................................................................................. 54
4-11 Coordination of Core Power States at the Package Level.............................................. 57
4-12 Targeted Memory State Conditions........................................................................... 62
5-1 Intel
®
Turbo Boost Technology Package Power Control Settings ................................... 69
5-2 Configurable Thermal Design Power (cTDP) Modes ..................................................... 71
5-3 Thermal Design Power (TDP) Specifications ............................................................... 73
5-4 Junction Temperature Specification .......................................................................... 73
5-5 Package Turbo Parameters...................................................................................... 74
5-6 Idle Power Specifications ........................................................................................ 75
6-1 Signal Description Buffer Types ............................................................................... 83
6-2 Memory Channel A Signals...................................................................................... 84
6-3 Memory Channel B Signals...................................................................................... 85
6-4 Memory Reference and Compensation ...................................................................... 86
6-5 Reset and Miscellaneous Signals .............................................................................. 86
6-6 PCI Express* Graphics Interface Signals ................................................................... 87
6-7 Embedded DisplayPort* Signals ............................................................................... 87
6-8 Intel
®
Flexible Display (Intel
®
FDI) Interface ............................................................ 87
6-9 Direct Media Interface (DMI) Signals – Processor to PCH Serial Interface....................... 88
6-10 Phase Lock Loop (PLL) Signals................................................................................. 88
6-11 Test Access Points (TAP) Signals.............................................................................. 88
6-12 Error and Thermal Protection Signals........................................................................ 89
6-13 Power Sequencing Signals ...................................................................................... 90
6-14 Processor Power Signals ......................................................................................... 91
6-15 Sense Signals ....................................................................................................... 91
6-16 Ground and Non-Critical to Function (NCTF) Signals ................................................... 92
6-17 Processor Internal Pull-Up / Pull-Down Resistors ........................................................ 92
7-1 IMVP7 Voltage Identification Definition ..................................................................... 94
7-2 VCCSA_VID Configuration ....................................................................................... 97
7-3 Signal Groups1...................................................................................................... 98
7-4 Storage Condition Ratings......................................................................................100
7-5 Processor Core (V
CC
) Active and Idle Mode DC Voltage and Current Specifications .........101
7-6 Processor Uncore (V
CCIO
) Supply DC Voltage and Current Specifications.......................103
7-7 Memory Controller (V
DDQ
) Supply DC Voltage and Current Specifications......................103
7-8 System Agent (V
CCSA
) Supply DC Voltage and Current Specifications ...........................103
7-9 Processor PLL (V
CCPLL
) Supply DC Voltage and Current Specifications ..........................104
7-10 Processor Graphics (V
AXG
) Supply DC Voltage and Current Specifications .....................104
7-11 DDR3 / DDR3L / DDR3L-RS Signal Group DC Specifications ........................................105
7-12 Control Sideband and TAP Signal Group DC Specifications ..........................................106
7-13 PCI Express* DC Specifications...............................................................................107
7-14 Embedded DisplayPort* DC Specifications ................................................................107
7-15 PECI DC Electrical Limits........................................................................................109
8-1 rPGA988B Processor Pin List by Pin Name ................................................................112
8-2 BGA1224 Processor Ball List by Ball Name................................................................125
8-3 BGA1023 Processor Ball List by Ball Name................................................................144
9-1 DDR Data Swizzling Table – Channel A ....................................................................168
9-2 DDR Data Swizzling Table for Package – Channel B ...................................................169