Datasheet
6 Datasheet, Volume 1
5.6.2 Digital Thermal Sensor ........................................................................... 78
5.6.2.1 Digital Thermal Sensor Accuracy (Taccuracy) ............................... 79
5.6.2.2 Fan Speed Control with Digital Thermal Sensor............................. 79
5.6.3 PROCHOT# Signal.................................................................................. 79
5.6.3.1 Bi-Directional PROCHOT# .......................................................... 79
5.6.3.2 Voltage Regulator Protection versus PROCHOT# ........................... 80
5.6.3.3 Thermal Solution Design and PROCHOT# Behavior........................ 80
5.6.3.4 Low-Power States and PROCHOT# Behavior................................. 80
5.6.3.5 THERMTRIP# Signal.................................................................. 81
5.6.3.6 Critical Temperature Detection ................................................... 81
5.6.4 On-Demand Mode .................................................................................. 81
5.6.4.1 MSR Based On-Demand Mode .................................................... 81
5.6.4.2 I/O Emulation-Based On-Demand Mode....................................... 81
5.6.5 Memory Thermal Management................................................................. 82
5.6.6 Platform Environment Control Interface (PECI) .......................................... 82
6 Signal Description................................................................................................... 83
6.1 System Memory Interface Signals ....................................................................... 84
6.2 Memory Reference and Compensation Signals ...................................................... 86
6.3 Reset and Miscellaneous Signals ......................................................................... 86
6.4 PCI Express*-based Interface Signals .................................................................. 87
6.5 Embedded DisplayPort* (eDP*) Signals ............................................................... 87
6.6 Intel
®
Flexible Display (Intel
®
FDI) Interface Signals............................................. 87
6.7 Direct Media Interface (DMI) Signals ................................................................... 88
6.8 Phase Lock Loop (PLL) Signals ............................................................................ 88
6.9 Test Access Points (TAP) Signals ......................................................................... 88
6.10 Error and Thermal Protection Signals................................................................... 89
6.11 Power Sequencing Signals.................................................................................. 90
6.12 Processor Power Signals .................................................................................... 91
6.13 Sense Signals................................................................................................... 91
6.14 Ground and Non-Critical to Function (NCTF) Signals .............................................. 92
6.15 Processor Internal Pull-Up / Pull-Down Resistors ................................................... 92
7 Electrical Specifications .......................................................................................... 93
7.1 Power and Ground Pins...................................................................................... 93
7.2 Decoupling Guidelines ....................................................................................... 93
7.2.1 Voltage Rail Decoupling .......................................................................... 93
7.2.2 PLL Power Supply .................................................................................. 93
7.3 Voltage Identification (VID)................................................................................ 94
7.4 System Agent (SA) Vcc VID ............................................................................... 97
7.5 Reserved or Unused Signals ............................................................................... 97
7.6 Signal Groups................................................................................................... 98
7.7 Test Access Port (TAP) Connection .....................................................................100
7.8 Component Storage Condition Specifications (Prior to Board Attach) .......................100
7.9 DC Specifications .............................................................................................101
7.9.1 Voltage and Current Specifications ..........................................................101
7.10 Platform Environmental Control Interface (PECI) DC Specifications .........................108
7.10.1 PECI Bus Architecture............................................................................108
7.10.2 PECI DC Characteristics .........................................................................109
7.10.3 Input Device Hysteresis .........................................................................109
8 Processor Pin, Signal, and Package Information ....................................................111
8.1 Processor Pin Assignments ................................................................................111
8.2 Package Mechanical Information ........................................................................158
9 DDR Data Swizzling................................................................................................167