Datasheet

Graphics, Video, and Display
Intel
®
Atom™ Processor E6xx Series Datasheet
99
Table 94. B0h: GVD.VCID – Vendor Capability ID
Size: 32 bit Default: 01070009h Power Well: Core
Access
PCI Configuration B:D:F 0:2:0
Offset Start:
Offset End:
B0h
Message Bus Port:
06h
Register Address: 2Ch
Bit Range Default Access Acronym Description
31 :24 01h RO VERSION VS: Identifies this as the first revision of the CAPID register definition.
23 :16 07h RO LENGTH
LEN: This field has the value 07h to indicate the structure length (8
bytes).
15 :8 00h RO
NEXT_CAPABIL
ITY_POINTER
If FD.MD is cleared, this reports 90h (MSI capability). If FD.MD is set, this
reports 00h (last item in the list).
7 :0 09h RO
CAPABILITY_ID
_CID
Identifies this as a vendor dependent capability pointers.
Table 95. B4h: GVD.VC – Vendor Capabilities
Size: 32 bit Default: 00000000h Power Well: Core
Access
PCI Configuration B:D:F 0:2:0
Offset Start:
Offset End:
B4h
Message Bus Port:
06h
Register Address: 2Dh
Bit Range Default Access Acronym Description
31 :0 0h RO RESERVED Reserved
Table 96. C4h: GVD.FD – Functional Disable
Size: 32 bit Default: C4h Power Well: Core
Access
PCI Configuration B:D:F 0:2:0
Offset Start:
Offset End:
C4h
Message Bus Port:
06h
Register Address: 31h
Bit Range Default Access Acronym Description
31 :2
000000
00h
RO RESERVED Reserved
1 0b RW MSI_DISABLE
MD: When set, the MSI capability pointer is not available - the item
which points to the MSI capability (the power management capability),
will instead indicate that this is the last item in the list.
00b RW
FUNCTION_DIS
ABLE
FD: When set, the function is disabled (configuration space is disabled).
When set, the GVD stops accepting any new requests on the SCL bus
including any new configuration cycle requests to clear this bit.