Datasheet

Graphics, Video, and Display
Intel
®
Atom™ Processor E6xx Series Datasheet
98
22 :20 000b RW
MULTIPLE_MES
SAGE_ENABLE
MME: This field is RW for software compatibility, but only a single
message is ever generated.
19 :17 000b RO
MULTIPLE_MES
SAGE_CAPABLE
MMC: This device is only single message capable.
16 0b RW MSI_ENABLE
MSIE: If set, MSI is enabled and traditional interrupts are not used to
generate interrupts. PCICMDSTS.BME must be set for an MSI to be
generated.
When 0, blocks the sending of a MSI interrupt and permits the sending of
a Message bus interrupt. (The interrupt status is not blocked from being
reflected in the PCICMDSTS.IS bit.)
When 1, permits sending of a MSI interrupt and blocks the sending of a
Message bus interrupt. (The interrupt status is not blocked from being
reflected in the PCICMDSTS.IS bit.)
15 :8 00h RO
POINTER_TO_N
EXT_CAPABILIT
Y
Indicates this is the last item in the list.
7 :0 05h RO
CAPABILITY_ID
_
CAPID: Indicates an MSI capability.
Table 92. 94h: GVD.MA – Message Address
Size: 32 bit Default: 00000000h Power Well: Core
Access
PCI Configuration B:D:F 0:2:0
Offset Start:
Offset End:
94h
Message Bus Port:
06h
Register Address: 25h
Bit Range Default Access Acronym Description
31 :2
000000
00h
RW ADDRESS
MA: Lower 32-bits of the system specified message address, always DW
aligned. When the GVD issues an MSI interrupt as a MEMWR on the SCL,
the memory address corresponds to the value of this field.
1 :0 00b RO RESERVED Reserved
Table 93. 98h: GVD.MD – Message Data
Size: 32 bit Default: 00000000h Power Well: Core
Access
PCI Configuration B:D:F 0:2:0
Offset Start:
Offset End:
98h
Message Bus Port:
06h
Register Address: 26h
Bit Range Default Access Acronym Description
31 :16 0000h RO RESERVED Reserved
15 :0 0000h RW DATA
MD: This 16-bit field is programmed by system software and is driven
onto the lower word of data during the data phase of the MSI write
transaction. When the GVD issues an MSI interrupt as a MEMWR on the
SCL, the write data corresponds to the value of this field.
Table 91. 90h: GVD.MSI_CAPID – Message Signaled Interrupts Capability ID and
Control Register (Sheet 2 of 2)
Size: 32 bit Default: 00000005h Power Well: Core
Access
PCI Configuration B:D:F 0:2:0
Offset Start:
Offset End:
90h
Message Bus Port:
06h
Register Address: 24h
Bit Range Default Access Acronym Description