Datasheet

Graphics, Video, and Display
Intel
®
Atom™ Processor E6xx Series Datasheet
97
Table 89. 5Ch: GVD.BSM – Base of Stolen Memory
Size: 32 bit Default: 00000000h Power Well: Core
Access
PCI Configuration B:D:F 0:2:0
Offset Start:
Offset End:
5Ch
Message Bus Port:
06h
Register Address: 17h
Bit Range Default Access Acronym Description
31 :20 000h RW
BASE_OF_STOL
EN_MEMORY
BSM: This register contains bits 31 to 20 of the base address of stolen
DRAM memory. When the GVD receives a VGA memory request
address[19:5] from the vrdunit or vrhunit, the GVD appends the base
address BSM[31:20] to form the full physical address to send to the
Bunit.
19 :0 00000h RO RESERVED Reserved
Table 90. 60h: GVD.MSAC – Multi Size Aperture Control
Size: 32 bit Default: 00020000h Power Well: Core
Access
PCI Configuration B:D:F 0:2:0
Offset Start:
Offset End:
60h
Message Bus Port:
06h
Register Address: 18h
Bit Range Default Access Acronym Description
31 :18 0000h RW SCRATCH Spare bits
17 :16 10b RW
UN_TRUSTED_
APERTURE_SIZ
E_UAS
This register determines the size of the graphics memory aperture and
untrusted space. by default the aperture size is 256 MB. Only BIOS writes
this register based on address allocation efforts. Drivers may read this
register to determine the correct aperture size. BIOS must restore this
data upon S3 resume. The value in this field affects the size of the
GMADR and the size of the GTTBAR that is formed and used by the GVD.
00 - Reserved.
01 - 512 MB. Bits 28 and 27 of GMADR are read-only, allowing 512 MB of
address space to be mapped. The un-trusted GTT is 512 kB.
10 - 256 MB. Bit 28 is read-write and bit 27 of GMADR is read-only
limiting the address space to 256 MB. The un-trusted GTT is 256 KB
11 - 128 MB. Bits 28 and 27 of GMADR are read-write limiting the
address space to 128 MB. The un-trusted GTT is 128 KB.
15 :0 0000h RW SCRATCH Spare bits
Table 91. 90h: GVD.MSI_CAPID – Message Signaled Interrupts Capability ID and
Control Register (Sheet 1 of 2)
Size: 32 bit Default: 00000005h Power Well: Core
Access
PCI Configuration B:D:F 0:2:0
Offset Start:
Offset End:
90h
Message Bus Port:
06h
Register Address: 24h
Bit Range Default Access Acronym Description
31 :24 00h RO RESERVED Reserved
23 0 RO
64_BIT_ADDRE
SS_CAPABLE
C64: 32-bit capable only.