Datasheet

Graphics, Video, and Display
Intel
®
Atom™ Processor E6xx Series Datasheet
96
Table 88. 50h: GVD.MGGC – Graphics Control
Size: 32 bit Default: 00300000h Power Well: Core
Access
PCI Configuration B:D:F 0:2:0
Offset Start:
Offset End:
50h
Message Bus Port:
06h
Register Address: 14h
Bit Range Default Access Acronym Description
31 :23 0 RO RESERVED
22 :20 011b RW
GRAPHICS_MO
DE_SELECT
GMS: This field is used to select the amount of memory pre-allocated to
support the graphics device in VGA (non-linear) and Native (linear)
modes. If graphics is disabled, this value must be programmed to 000h.
000 = No memory pre-allocated. Graphics does not claim VGA cycles
(Mem and IO), and CC.SCC is 80h.
001 = DVMT (UMA) mode, 1 MB of memory pre-allocated for frame
buffer
010 = DVMT (UMA) mode, 4 MB of memory pre-allocated for frame
buffer
011 = DVMT (UMA) mode, 8 MB of memory pre-allocated for frame
buffer
100 = DVMT (UMA) mode, 16 MB of memory pre-allocated for frame
buffer
101 = DVMT (UMA) mode, 32 MB of memory pre-allocated for frame
buffer
110 = DVMT (UMA) mode, 48 MB of memory pre-allocated for frame
buffer
111 = DVMT (UMA) mode, 64 MB of memory pre-allocated for frame
buffer
When GMS not equal to 000 (and VD=0) the GVD will check if the SCL
address scldown3_address[31:0] is in the VGA memory range. (The VGA
memory range is A0000h to BFFFFh.) If there is a match and MSE = 1
and the SCL command is either a MEMRD or MEMWR, the GVD will initiate
an RMdwvgamemen_cr cycle on the RMbus. If the RMbus returns a hit
the GVD will select the command. As well, when 0 the GVD will check if
scldown3_address[15:0] is one of the VGA IO register range. (The VGA
IO range is 03B0h - 03BBh and 03C0h - 03DFh.) If there is a match and
IOSE = 1 and the SCL command is either an IORD or IOWR, the GVD will
initiate a (VGA) register cycle on the RMbus. If the RMbus returns a hit
the GVD will select the command.When GMS is equal to 000, the GVD will
not check if the SCL address is in the VGA memory range or in the VGA
IO register address range. Also, when GMS is set to 3’b000, then
CC[15:8] is changed to 8’h80 from 8’h00.
19 :18 0 RO RESERVED Reserved
17 0b RW VGA_DISABLE
VD: When set, VGA memory or I/O cycles are not claimed, and CC.SCC is
set to 80h. When cleared, VGA memory and I/O cycles are enabled, and
CC.SCC is set to 00h.
When 0 (and GMS not equal to 000), the GVD will check if the SCL
address scldown3_address[31:0] is in the VGA memory range. (The VGA
memory range is A0000h to BFFFFh.) If there is a match and MSE=1 and
the SCL command is either a MEMRD or MEMWR, the GVD will initiate an
RMdwvgamemen_cr cycle on the RMbus. If the RMbus returns a hit the
GVD will select the command. As well, when 0 the GVD will check if
scldown3_address[15:0] is one of the VGA IO register range. (The VGA
IO range is 03B0h - 03BBh and 03C0h - 03DFh.) If there is a match and
IOSE = 1 and the SCL command is either an IORD or IOWR, the GVD will
initiate a (VGA) register cycle on the RMbus. If the RMbus returns a hit
then the command will be claimed by the GVD. When 1, the GVD will not
check if the SCL address is in the VGA memory range or in the VGA IO
register address range. Also, when the field is set 1’b1 and GMS =
3’b000, then CC[15:8] is changed to 8’h80 from 8’h00.
16 :0 00000h RO RESERVED Reserved