Datasheet

Graphics, Video, and Display
Intel
®
Atom™ Processor E6xx Series Datasheet
94
Table 83. 18h: GVD.GMADR – Graphics Memory Address Range
Size: 32 bit Default: 00000000h Power Well: Core
Access
PCI Configuration B:D:F 0:2:0
Offset Start:
Offset End:
18h
Message Bus Port:
06h
Register Address: 06h
Bit Range Default Access Acronym Description
31 :29 0h RW BASE_ADDRESS
BA: Set by the OS, these bits correspond to address signals [31:28]. The
GVD will compare the SCL address scldown3_address[31:29,28, or 27]
with GMADR[31:29,28, or 27], respectively. (Whether the comparison is
31:29, 31:28 or 31:27 depends on the value of MSAC[17:16].) If there is
a match, and MSE =1 and the SCL command is either a MEMRD or
MEMWR, the GVD will select the command (i.e. issue a scldown3_hit).
The GMADR is to be used for the graphics cluster (GFX) tiled memory
space.
28 0b RWL
512_MB_ADDR
ESS_MASK
M512M: This bit is either part of the Memory Base Address (RW) or part
of the Address Mask (RO), depending on the value of MSAC.UAS. If this
bit is used in the address comparison, the address space is limited to 256
MB.
27 0b RWL
256_MB_ADDR
ESS_MASK
M256M: This bit is either part of the Memory Base Address (RW) or part
of the Address Mask (RO), depending on the value of MSAC.UAS. If this
bit is used in the address comparison, the address space is limited to 128
MB.
26 :1 0h RO RESERVED Reserved
00b RO
RESOURCE
_TYPE_RTE
Indicates a request for memory space.
Table 84. 1Ch: GVD.GTTADR – Graphics Translation Table Address Range
Size: 32 bit Default: 00000000h Power Well: Core
Access
PCI Configuration B:D:F 0:2:0
Offset Start:
Offset End:
1Ch
Message Bus Port:
06h
Register Address: 07h
Bit Range Default Access Acronym Description
31 :19 0h RW BASE_ADDRESS
BA: Set by the OS, these bits correspond to address signals [31:19]. The
GVD will compare the SCL address scldown3_address[31:19,18, or 17]
with GTTBAR[31:19,18, or 17], respectively. (Whether the comparison is
31:19, 31:18 or 31:17 depends on the value of MSAC[17:16].) If there is
a match, and MSE = 1 and the SCL command is either a MEMRD or
MEMWR, the GVD will select the command (i.e. issue a scldown3_hit).
The GVD will then issue a memory read/write (via the LP arbiter
RequestGB1 interface with Bunit). The address of the read/write will be
an offset from Page Table Base Address[31:1] defined in MMIO register
02020h.
18 0b RWL
512_KB_ADDRE
SS_MASK
M512K: This bit is either part of the GTT Base Address (RW) or part of
the Address Mask (RO), depending on the value of MSAC.UAS. If this bit
is used in the address comparison, the address space is limited to 256
kB.
17 0b RWL
256_KB_ADDRE
SS_MASK
M256K: This bit is either part of the GTT Base Address (RW) or part of
the Address Mask (RO), depending on the value of MSAC.UAS. If this bit
is used in the address comparison, the address space is limited to 128
kB.
16 :1 0h RO RESERVED Reserved
0 0b RO BASE_ADDRESS RTE: Indicates a request for memory space.