Datasheet

Graphics, Video, and Display
Intel
®
Atom™ Processor E6xx Series Datasheet
93
Table 81. 10h: GVD.MMADR – Memory Mapped Address Range
Size: 32 bit Default: 00000000h Power Well: Core
Access
PCI Configuration B:D:F 0:2:0
Offset Start:
Offset End:
10h
Message Bus Port:
06h
Register
Address:
04h
Bit Range Default Access Acronym Description
31 :20 000h RW BASE_ADDRESS
BA: Set by the OS, these bits correspond to address signals [31:20].
The GVD will compare the SCL address scldown3_address[31:20] with
MMADR[31:20]. If there is a match, and PCICMDSTS[1] = MSE = 1 and
the SCL command is either a MEMRD or MEMWR, the GVD will select
the command and present it on the RMbus. The MMADR is to be used
for register programming the GVD memory interface registers, the
display controller registers, the graphics cluster (GFX) registers, the
video decode (VED) registers, the video encode (VEC) registers, and
the video processing block (VPB) registers. If the display controller
registers don’t assert claim, then GVD will report a miss on the SCL
bus. For all other register address that are part of this address range,
GVD will assert a hit on the SCL bus.
19 :1 0000h RO RESERVED Reserved
0 0b RO RESOURCE_TYPE RTE: Indicates a request for memory space.
Table 82. 14h: GVD.GFX_IOBAR – I/O Base Address
Size: 32 bit Default: 00000001h Power Well: Core
Access
PCI Configuration B:D:F 0:2:0
Offset Start:
Offset End:
14h
Message Bus Port:
06h
Register Address: 05h
Bit Range Default Access Acronym Description
31 :16 0000h RO RESERVED Reserved
15 :3 0000h RW BASE_ADDRESS
BA: Set by the OS, these bits correspond to address signals [15:3]. The
GVD will compare the SCL address scldown3_address[15:3] with
GFX_IOBAR[15:3]. If there is a match, and PCICMDSTS[0] = IOSE = 1
and the SCL command is either an IORD or IOWR, the GVD will select the
command (i.e. issue a scldown3_hit). The GFX_IOBAR is to be used for
register programming the GVD memory interface registers, the display
controller registers, the graphics cluster (GFX) registers, the video
decode (VED) registers, the video encode (VEC) registers, and the video
processing block (VPB) registers using the indirect register access
method. The GFX_IOBAR is to be used for GTT write on SCL using the
indirect access method.
2 :1 0h RO RESERVED Reserved
01h RO
RESOURCE_
TYPE_RTE
Indicates a request for I/O space.