Datasheet
Graphics, Video, and Display
Intel
®
Atom™ Processor E6xx Series Datasheet
92
00b RW
IO_SPACE_ENA
BLE
IOSE: When set, accesses to this device’s I/O space is enabled. When 1,
the GVD will check if scldown3_address[15:0] is in the VGA IO range.
(The VGA IO range is 03B0h - 03BBh and 03C0h - 03DFh.) As well, the
GVD will check scldown3_address[15:3] with GFX_IOBAR[15:3]. If there
is a match (with VGA IO address range or GFX_IOBAR) and if the SCL
command is either an IORD or IOWR, the GVD will select the command
(i.e. issue a scldown3_hit). Care should be taken in setting up
GFX_IOBAR that more than 1 match is not made as this will result in
unpredictable behavior. When 0, the GVD will not select a IORD or IOWR
SCL command.
Table 79. 08h: GVD.RIDCC - Revision Identification and Class Code
Size: 32 bit Default: Power Well: Core
Access
PCI Configuration B:D:F 0:2:0
Offset Start:
Offset End:
08h
Message Bus Port:
06h
Register Address: 02h
Bit Range Default Access Acronym Description
31 :24 03h RO
BASE_CLASS_C
ODE
BCC: Indicates a display controller.
23 :16 00h RO
SUB_CLASS_C
ODE
When MGGC[1] = VD = 0b (default), this value is 00h. When MGGC[1] =
VD = 0b or when MGGC[6:4] = GMS = 000b, this value is 80h.
15 :8 00h RO
PROGRAMMING
_INTERFACE
PI: Indicates a display controller.
7:0
Refer to
bit
descript
ion
RO REVISION_ID
Revision Identification Number: This is an 8-bit value that indicates
the revision identification number for the device. For the B-0 Stepping,
this value is 03h. For B-1 Stepping, this value is 05h.
Table 78. 04h: GVD.PCICMDSTS – PCI Command and Status Register (Sheet 2 of 2)
Size: 32 bit Default: 00100000h Power Well: Core
Access
PCI Configuration B:D:F 0:2:0
Offset Start:
Offset End:
04h
Message Bus Port:
06h
Register Address: 01h
Bit Range Default Access Acronym Description
Table 80. 0Ch: GVD.HDR – Header Type
Size: 32 bit Default: 00000000h Power Well: Core
Access
PCI Configuration B:D:F 0:2:0
Offset Start:
Offset End:
0Ch
Message Bus Port:
06h
Register Address: 03h
Bit Range Default Access Acronym Description
31 :24 00h RO RESERVED Reserved
23 0b RO
MULTI_FUNCTI
ON_STATUS
MFUNC: Integrated graphics is a single function.
22 :16 00h RO HEADER_CODE HDR: Indicates a type 0 header format.
15 :0 RO RESERVED Reserved