Datasheet

Graphics, Video, and Display
Intel
®
Atom™ Processor E6xx Series Datasheet
91
Table 77. 00h: GVD.ID – D2: PCI Device and Vendor ID Register
Size: 32 bit Default: 41088086h Power Well: Core
Access
PCI Configuration B:D:F 0:2:0
Offset Start:
Offset End:
00h
01h
Message Bus Port:
06h
Register Address: 00h
Bit Range Default Access Acronym Description
31 :20 410h RO
DIDH: Identifier assigned to the Device 2 Graphics PCI device.
Bits[31:20] of this register are strapped at the processor top level.
19 :16
fus_Gfx
DevID_
nczfwoh
[3:0]
RO
DIDL: Identifier assigned to the Device 2 Graphics PCI device.
Bits[19:16] of this register are determined by fuse
fus_GfxDevID_nczfwoh.
15 :0 8086h RO VID: PCI standard identification for Intel.
Table 78. 04h: GVD.PCICMDSTS – PCI Command and Status Register (Sheet 1 of 2)
Size: 32 bit Default: 00100000h Power Well: Core
Access
PCI Configuration B:D:F 0:2:0
Offset Start:
Offset End:
04h
Message Bus Port:
06h
Register Address: 01h
Bit Range Default Access Acronym Description
31 :21 0h RO RESERVED Reserved
20 1b RO
CAPABILITY_LI
ST
CAP: Indicates that the CAPPOINT register at 34h provides an offset into
PCI Configuration Space containing a pointer to the location of the first
item in the list.
19 0b RO
INTERRUPT_ST
ATUS
IS: Reflects the state of the interrupt in the graphics device. Is set to 1 if
the aggregate display/gfx/ved/vpb/vec interrupt (as determined by IIR
and IER memory interface registers) is set to 1. Otherwise is set to 0.
18 :16 0h RO RESERVED Reserved
15 :11 0000b RO RESERVED Reserved
10 0b RW
INTERRUPT_DI
SABLE
ID: When 1, blocks the sending of a Message bus interrupt. The interrupt
status is not blocked from; being reflected in PCICMDSTS.IS. When 0,
permits the sending of a Message bus interrupt.
9:3
000000
0b
RO RESERVED Reserved
20b RW
BUS_MASTER_
ENABLE
BME: Enables GVD to function as a PCI compliant master. When 0, blocks
the sending of MSI interrupts. When 1, permits the sending of MSI
interrupts.
10b RW
MEMORY_SPAC
E_ENABLE
MSE: When set, accesses to this device’s memory space is enabled.
When 1, the GVD will compare scldown3_address[31:20] with;
MMADR[31:20]. As well, GVD will compare the address
scldown3_address[31:29,28, or 27] with GMADR[31:29,28, or 27],
respectively. (Whether the comparison is 31:29, 31:28 or 31:27 depends
on the value of MSAC[17:16].) As well, the GVD will check if
scldown3_address[31:0] is in the VGA memory range. (The VGA memory
range is A0000h to BFFFFh). If there is a match (with MMADR, or
GMADR, or VGA memory address range) and if the SCL command is
either a MEMRD or MEMWR, the GVD will select the command (i.e. issue
a scldown3_hit). Care should be taken in setting up MMADR and GMADR
that more than 1 match is not made as this will result in unpredictable
behavior. When 0, the GVD will not select a MEMRD or MEMWR SCL
command.