Datasheet
Contents
Intel
®
Atom™ Processor E6xx Series Datasheet
9
11.0 ACPI Devices......................................................................................................... 201
11.1 8254 Timer .................................................................................................... 201
11.1.1 Counter 0, System Timer ...................................................................... 201
11.1.2 Counter 1, Refresh Request Signal.......................................................... 201
11.1.3 Counter 2, Speaker Tone....................................................................... 201
11.1.4 Timer I/O Registers .............................................................................. 201
11.1.5 Offset 43h: TCW - Timer Control Word Register........................................ 201
11.1.5.1 Read Back Command .............................................................. 202
11.1.5.2 Counter Latch Command.......................................................... 203
11.1.5.3 Offset 40h, 41h, 42h: Interval Timer Status Byte Format Register. 203
11.1.5.4 Offset 40h, 41h, 42h: Counter Access Ports Register ................... 204
11.1.6 Timer Programming.............................................................................. 204
11.1.7 Reading from the Interval Timer............................................................. 205
11.1.7.1 Simple Read........................................................................... 205
11.1.7.2 Counter Latch Command.......................................................... 205
11.1.7.3 Read Back Command .............................................................. 206
11.2 High Precision Event Timer ............................................................................... 206
11.2.1 Registers............................................................................................. 206
11.2.1.1 Offset 000h: GCID – General Capabilities and ID......................... 207
11.2.1.2 Offset 010h: GC – General Configuration ................................... 207
11.2.1.3 Offset 020h: GIS – General Interrupt Status............................... 208
11.2.1.4 Offset 0F0h: MCV – Main Counter Value..................................... 208
11.2.1.5 Offset 100h, 120h, 140h: T[0-2]C – Timer [0-2] Config and
Capabilities............................................................................ 208
11.2.1.6 Offset 108h, 128h, 148h: T[0-2]CV – Timer [0-2] Comparator
Value .................................................................................... 209
11.2.2 Theory Of Operation ............................................................................. 210
11.2.2.1 Non-Periodic Mode – All timers ................................................. 210
11.2.2.2 Periodic Mode – Timer 0 only.................................................... 211
11.2.2.3 Interrupts.............................................................................. 211
11.2.2.4 Mapping Option #2: Standard Option (GC.LRE cleared)................ 212
11.3 8259 Interrupt Controller ................................................................................. 212
11.3.1 Overview ............................................................................................ 212
11.3.2 I/O Registers....................................................................................... 213
11.3.2.1 Offset 20h, A0h: ICW1 – Initialization Command Word 1.............. 213
11.3.2.2 Offset 21h, A1h: ICW2 – Initialization Command Word 2.............. 214
11.3.2.3 Offset 21h: MICW3 – Master Initialization Command Word 3 ........ 215
11.3.2.4 Offset A1h: SICW3 – Slave Initialization Command Word 3........... 215
11.3.2.5 Offset 21h, A1h: ICW4 – Initialization Command Word 4 Register . 215
11.3.2.6 Offset 21h, A1h: OCW1 – Operational Control Word 1 (Interrupt
Mask).................................................................................... 216
11.3.2.7 Offset 20h, A0h: OCW2 – Operational Control Word 2.................. 216
11.3.2.8 Offset 4D0h: ELCR1 – Master Edge/Level Control ........................ 217
11.3.2.9 Offset 4D1h: ELCR2 – Slave Edge/Level Control.......................... 218
11.3.3 Interrupt Handling................................................................................ 218
11.3.3.1 Generating............................................................................. 218
11.3.3.2 Acknowledging ....................................................................... 218
11.3.3.3 Hardware/Software Interrupt Sequence ..................................... 219
11.3.4 Initialization Command Words (ICW) ...................................................... 219
11.3.4.1 ICW1 .................................................................................... 219
11.3.4.2 ICW2 .................................................................................... 220
11.3.4.3 ICW3 .................................................................................... 220
11.3.4.4 ICW4 .................................................................................... 220
11.3.5 Operation Command Words (OCW)......................................................... 220
11.3.6 Modes of Operation .............................................................................. 220
11.3.6.1 Fully Nested Mode................................................................... 220
11.3.6.2 Special Fully Nested Mode........................................................ 221