Datasheet

Graphics, Video, and Display
Intel
®
Atom™ Processor E6xx Series Datasheet
89
A maximum pixel clock of 160 MHz is supported on the SDVO interface.
7.5.2.4 SDVO DVI/HDMI
DVI (and HDMI), a 3.3-V interface standard supporting the TMDS protocol, is a prime
candidate for SDVO. The Intel
®
Atom™ Processor E6xx Series provides an unscaled
mode where the display data is centered within the attached display area. Monitor Hot
Plug functionality is supported.
7.5.2.4.1 SDVO LVDS
The Intel
®
Atom™ Processor E6xx Series can use the SDVO port to drive an LVDS
transmitter. Flat Panel is a fixed resolution display. The processor supports panel fitting
in the transmitter, receiver or an external device, but has no native panel fitting
capabilities. The processor provides an unscaled mode where the display data is
centered within the attached display area. Scaling in the LVDS transmitter through the
SDVO stall input pair is also supported.
7.5.2.4.2 SDVO TV-Out
The SDVO port supports both standard and high-definition TV displays in a variety of
formats. The SDVO port generates the proper blank and sync timing, but the external
encoder is responsible for generation of the proper format signal and output timings.
The processor will support NTSC/PAL/SECAM standard definition formats. The
processor will generate the proper timing for the external encoder. The external
encoder is responsible for generation of the proper format signal.
7.5.2.4.3 Flicker Filter and Overscan Compensation
The overscan compensation scaling and the flicker filter is done in the external TV
encoder chip. Care must be taken to allow for support of TV sets with high performance
de-interlacers and progressive scan displays connected to by way of a non-interlaced
signal. Timing will be generated with pixel granularity to allow more overscan ratios to
be supported.
7.6 Control Bus
The SDVO port defines a two-wire (SDVO_CTRLCLK and SDVO_CTRLDATA)
communication path between the SDVO device and the processor. Traffic destined for
the PROM or DDC will travel across the control bus, and will then require the SDVO
device to act as a switch and direct traffic from the control bus to the appropriate
receiver. The control bus is able to operate at up to 1 MHz.
Display Pipe B is configured to use the SDVO port. The SDVO port can support a variety
of display types (VGA, LVDS, DVI, TV-Out, etc.) by an external SDVO device. SDVO
devices translate SDVO protocol and timings to the desired display format and timings.
A maximum pixel clock of 160 MHz is supported on the SDVO interface.