Datasheet

Graphics, Video, and Display
Intel
®
Atom™ Processor E6xx Series Datasheet
88
transmitter port at the dot clock frequency, which is determined by the panel timing
requirements. The serialized output of LVDS is running at the serial clock of 7x dot
clock frequency.
The transmitter can operate in a variety of modes and supports several data formats.
The serializer supports 6-bit or 8-bit color per lane (for 18-bit and 24-bit color
respectively) and single-channel operating modes. The display stream from the display
pipe is sent to the LVDS transmitter port at the dot clock frequency, which is
determined by the panel timing requirements. The output of LVDS is running at a fixed
multiple of the dot clock frequency.
The single LVDS channel can take 18 or 24 bits of RGB pixel data plus 3 bits of timing
control (HSYNC/VSYNC/DE) and output them on four differential data pair outputs.
This display port is normally used in conjunction with the pipe functions of panel up-
scaling and 6-to 8-bit dither. This display port is also used in conjunction with the panel
power sequencing and additional associated functions.
When enabled, the LVDS constant current drivers consume significant power. Individual
pairs or sets of pairs can be selected to be powered down when not being used.
However, when disabled, individual or sets of pairs will enter a low power state. When
the port is disabled, all pairs enters a low power mode. The panel power sequencing
can be set to override the selected power state of the drivers during power sequencing.
7.5.2.2 LVDS Backlight Control
To support LVDS Backlight Control, the Intel
®
Atom™ Processor E6xx Series will
generate five types of messages to the display cluster. The display cluster will in turn
drive VDDEN and BKLTEN and modulate the duty cycle before driving it out through
BKLTCTL. These three signals are multiplexed with the normal GPIO pins under the
LVDS_CTL_MODE (address to be defined). The DDC_CLK and DDC_DATA is emulated
through software.
7.5.2.3 SDVO Digital Display Port
Display Pipe B is configured to use the SDVO port. The SDVO port can support a variety
of display types (VGA, LVDS, DVI, TV-Out, etc.) by an external SDVO device. SDVO
devices translate SDVO protocol and timings to the desired display format and timings.
Figure 8. LVDS Control Signal Solution
Intel
®
Atom™
Processor E6xx
Series
LVDS Signals
LVD_DATAP_[3:0]
LVD_DATAN_[3:0]
LVD_CLKP
LVD_CLKN
GPIO
Interface
GPIO_SUS[3]
GPIO_SUS[1]
GPIO_SUS[0]
GPIO_SUS[4]
GPIO_SUS[2]
Control
Signals
DDC_CLK
DDC_DATA
VDDEN
BKLTEN
BKLTCTL