Datasheet

Graphics, Video, and Display
Intel
®
Atom™ Processor E6xx Series Datasheet
76
3D peak performance
Fill rate: two pixels per clock
Vertex rate: One triangle 15 clocks (transform only)
Vertex/Triangle ratio average = 1 vtx/tri, peak 0.5 vtx/tri
Texture maximum size = 2048 x 2048
Programmable 4x multi-sampling anti-aliasing (MSAA)
—Rotated grid
ISP performance related to AA mode, TSP performance unaffected by AA mode
Optimized memory efficiency using multi-level cache architecture
7.2.2 Shading Engine Key Features
The unified pixel/vertex shader engine supports a broad range of instructions.
Unified programming model
Multi-threaded with four concurrently running threads
Zero-cost swapping in/out of threads
Cached program execution model – unlimited program size
Dedicated pixel processing instructions
Dedicated vertex processing instructions
2048 32-bit registers
SIMD pipeline supporting operations in:
32-Bit IEEE Float
2-way, 16-bit fixed point
4-way, 8-bit integer
32-bit, bit-wise (logical only)
Static and dynamic flow control
Subroutine calls
—Loops
Conditional branches
Zero-cost instruction predication
Procedural geometry
Allows generation of more primitives on output compared with input data
Effective geometry compression
High order surface support
External data access
Permits reads from main memory by cache (can be bypassed)
Permits writes to main memory
Data fence facility provided
Dependent texture reads