Datasheet

Memory Controller
Intel
®
Atom™ Processor E6xx Series Datasheet
74
§ §
A[13] R0 R0 R0 R0 R0 R0 R0 R0
A[12] B0 B0 B0 B0 B0 B0 B0 B0
A[11] C9 C9 C9 C9 C9 C9 C9 C9
A[10] C8 C8 C8 C8 C8 C8 C8 C8
A[9] C7 C7 C7 C7 C7 C7 C7 C7
A[8] C6 C6 C6 C6 C6 C6 C6 C6
A[7] C5 C5 C5 C5 C5 C5 C5 C5
A[6] C4 C4 C4 C4 C4 C4 C4 C4
A[5] C3 C3 C3 C3 C3 C3 C3 C3
A[4] C2 C2 C2 C2 C2 C2 C2 C2
A[3] C1 C1 C1 C1 C1 C1 C1 C1
A[2] C0 C0 C0 C0 C0 C0 C0 C0
Table 71. DRAM Address Decoder (Sheet 2 of 2)
Notes:
1. R = Row Address bit
2. C = Column Address bit
3. B = Bank Select bit (M_BS[2:0])
4. RS = Rank select. If RS = 0, then Chip Select bit (M_CS[0]#). If RS = 1, the Chip Select bit
(M_CS[1]#).