Datasheet

Memory Controller
Intel
®
Atom™ Processor E6xx Series Datasheet
73
6.9 Address Mapping and Decoding
For any rank, the address range it implements is mapped into the physical address
regions of the devices on that rank. This is addressable by bank (B), row (R), and
column (C) addresses. Once a rank is selected as described above, the range that it is
implementing is mapped into the device’s physical address as described in Table 71.
Table 71. DRAM Address Decoder (Sheet 1 of 2)
Tech DDR2 DDR2 DDR2 DDR2 DDR2 DDR2 DDR2 DDR2
Rank Size 128 MB 128 MB 256 MB 256 MB 512 MB 512 MB 512 MB 1 GB
Density 256 Mb 512 Mb 512 Mb 1 Gb 1 Gb 1 Gb 2 Gb 2 Gb
Width x8 x16 x8 x16 x8 x8 x16 x8
Bank Bits 22233333
Row Bits 13 13 14 13 14 14 14 15
Column Bits 10 10 10 10 10 10 10 10
A[31]
A[30] RS
A[29] RS RS R14
A[28] RS RS R13 R13 R13 R13
A[27] RSRSR13B2B2B2B2B2
A[26] R12 R12 R12 R12 R12 R12 R12 R12
A[25] R11 R11 R11 R11 R11 R11 R11 R11
A[24] R10 R10 R10 R10 R10 R10 R10 R10
A[23] R9 R9 R9 R9 R9 R9 R9 R9
A[22] R8 R8 R8 R8 R8 R8 R8 R8
A[21] R7 R7 R7 R7 R7 R7 R7 R7
A[20] B1 B1 B1 B1 B1 B1 B1 B1
A[19] R6 R6 R6 R6 R6 R6 R6 R6
A[18] R5 R5 R5 R5 R5 R5 R5 R5
A[17] R4 R4 R4 R4 R4 R4 R4 R4
A[16] R3 R3 R3 R3 R3 R3 R3 R3
A[15] R2 R2 R2 R2 R2 R2 R2 R2
A[14] R1 R1 R1 R1 R1 R1 R1 R1
Notes:
1. R = Row Address bit
2. C = Column Address bit
3. B = Bank Select bit (M_BS[2:0])
4. RS = Rank select. If RS = 0, then Chip Select bit (M_CS[0]#). If RS = 1, the Chip Select bit
(M_CS[1]#).