Datasheet

Memory Controller
Intel
®
Atom™ Processor E6xx Series Datasheet
72
6.7 Supported DRAM Devices
6.8 Supported Rank Configurations
Table 69. Supported DDR2 DRAM Devices
DRAM Density Data Width Banks Bank Address Row Address Column Address Page Size
256 Mb x8 4 BA[1:0] MA[12:0] MA[9:0] 1 kB
512 Mb x8 4 BA[1:0] MA[13:0] MA[9:0] 1 kB
1 Gb x8 8 BA[2:0] MA[13:0] MA[9:0] 1 kB
2 Gb x8 8 BA[2:0] MA[14:0] MA[9:0] 1 kB
512 Mb x16 4 BA[1:0] MA[12:0] MA[9:0] 2 kB
1 Gb x16 8 BA[2:0] MA[12:0] MA[9:0] 2 kB
2 Gb x16 8 BA[2:0] MA[13:0] MA[9:0] 2 kB
Table 70. Memory Size Per Rank
Memory
Size/Rank
DRAM
Chips/Rank
DRAM Chip
Density
DRAM Chip
Data Width
Banks/C
hip
Page
Size/Chip
Page Size @
32-bit Data Bus
128 MB 4 256 Mb x8 4 1 kB
4 kB = 1 kB x 4
Chips
256 MB 4 512 Mb x8 4 1 kB
4 kB = 1 kB x 4
Chips
512 MB 4 1 Gb x8 8 1 kB
4 kB = 1 kB x 4
Chips
1 GB 4 2 Gb x8 8 1 kB
4 kB = 1 kB x 4
Chips
128 MB 2 512 Mb x16 4 2 kB
4 kB = 2 kB x 2
Chips
256 MB 2 1 Gb x16 8 2 kB
4 kB = 2 kB x 2
Chips
512 MB 2 2 Gb x16 8 2 kB
4 kB = 2 kB x 2
Chips