Datasheet

Memory Controller
Intel
®
Atom™ Processor E6xx Series Datasheet
70
6.4.1 Powerdown Modes
The memory controller employs aggressive use of memory power management
features. When a rank is not being accessed, the CKE for that rank is deasserted,
bringing the devices into a Power Down state. The memory controller supports Fast
Power Down for DDR2 DRAMs.
6.4.2 Self Refresh Mode
Self Refresh can be used to retain data in the DRAM devices, even if the remainder of
the system is powered down. When the memory is in Self Refresh, the memory
controller disables all output signals except the CKE signals. The controller will enter
Self Refresh as part of the S3 sequence, and stay in Self Refresh until an exit sequence
is initiated.
There are two Self Refresh modes that the memory controller provides: Shallow and
Deep. Deep Self Refresh provides for additional power savings over Shallow Self
Refresh, but at the cost of increased exit latency. The power savings for Deep Self
Refresh are achieved by optimizations in power gating and clock gating for the DDRIO
PHY circuits. Both Self Refresh modes are transparent to the DRAM device, and the
entry and exit commands are the same.
6.4.3 Dynamic Self Refresh Mode
The memory controller also supports Dynamic Self Refresh when the Intel
®
Atom™
Processor E6xx Series is in C2–C6 idle states. It wakes the memory from Self Refresh
whenever memory access is needed; then it re-enters Self Refresh mode when no
more requests are needed. Both Deep and Shallow Self Refresh modes are supported
for Dynamic Self Refresh, selected by means of a configuration bit .
6.4.4 Page Management
The memory controller is capable of closing pages after these pages have been idle for
an optimized period of time. This page management mechanism provides both power
and performance benefits. From a performance standpoint, it helps since it can reduce
the number of page misses encountered. From a power perspective, it allows the
memory devices to reach the precharge power management state (power down when
all banks are closed), which has better power saving characteristics on most memory
devices than when the pages are left open and the device is in Active Power-Down
mode.
6.5 Refresh Mode
The memory controller handles all DRAM refresh operations when the device is not in
Self Refresh. To reduce the performance impact of DRAM refreshes, the memory
controller can wait until eight refreshes are required and then issue all of these
refreshes. This provides some increase in efficiency (overall lower percentage of impact
to the available bandwidth), but there will also be a longer period of time that the
memory will be unavailable, roughly 8 x t
RFC
(refresh cycle time).