Datasheet

Contents
Intel
®
Atom™ Processor E6xx Series Datasheet
7
8.2.2.9 SLCAP — Slot Capabilities ........................................................ 127
8.2.2.10 SLCTL — Slot Control .............................................................. 127
8.2.2.11 SLSTS — Slot Status ............................................................... 128
8.2.2.12 RCTL — Root Control............................................................... 129
8.2.2.13 RCAP — Root Capabilities......................................................... 129
8.2.2.14 RSTS — Root Status................................................................ 129
8.2.3 PCI Bridge Vendor Capability ................................................................. 130
8.2.3.1 SVCAP — Subsystem Vendor Capability ..................................... 130
8.2.3.2 SVID — Subsystem Vendor IDs ................................................ 130
8.2.4 PCI Power Management Capability.......................................................... 130
8.2.4.1 PMCAP — Power Management Capability ID................................ 131
8.2.4.2 PMC — PCI Power Management Capabilities................................ 131
8.2.4.3 PMCS — PCI Power Management Control And Status ................... 131
8.2.5 Port Configuration ................................................................................ 132
8.2.5.1 MPC — Miscellaneous Port Configuration .................................... 133
8.2.5.2 SMSCS — SMI / SCI Status...................................................... 134
8.2.6 Miscellaneous Configuration................................................................... 135
8.2.6.1 FD — Functional Disable .......................................................... 135
9.0 Intel
®
High Definition Audio
β
D27:F0..................................................................... 137
9.1 Overview ....................................................................................................... 137
9.2 Docking ......................................................................................................... 137
9.2.1 Dock Sequence .................................................................................... 138
9.2.2 Undock Sequence................................................................................. 139
9.2.3 Relationship Between HDA_DOCKRST_B and HDA_RST_B.......................... 139
9.2.4 External Pull-Ups/Pull-Downs ................................................................. 140
9.3 PCI Configuration Register Space ...................................................................... 140
9.3.1 Registers............................................................................................. 140
9.3.1.1 Offset 00h: VID – Vendor Identification ..................................... 142
9.3.1.2 Offset 02h: DID – Device Identification...................................... 142
9.3.1.3 Offset 04h: PCICMD – PCI Command Register ............................ 142
9.3.1.4 Offset 06h: PCISTS – PCI Status Register .................................. 143
9.3.1.5 Offset 08h: RID – Revision Identification Register ....................... 143
9.3.1.6 Offset 09h: CC – Class Codes Register....................................... 143
9.3.1.7 Offset 0Ch: CLS - Cache Line Size Register................................. 144
9.3.1.8 Offset 0Dh: LT – Latency Timer Register.................................... 144
9.3.1.9 Offset 0Eh: HEADTYP - Header Type Register ............................. 144
9.3.1.10 Offset 10h: LBAR – Lower Base Address Register ........................ 144
9.3.1.11 Offset 14h: UBAR – Upper Base Address Register........................ 145
9.3.1.12 Offset 2Ch: SVID—Subsystem Vendor Identifier.......................... 145
9.3.1.13 Offset 2Eh: SID—Subsystem Identifier....................................... 146
9.3.1.14 Offset 34h – CAP_PTR – Capabilities Pointer Register................... 146
9.3.1.15 Offset 3Ch – INTLN: Interrupt Line Register ............................... 146
9.3.1.16 Offset 3Dh – INTPN—Interrupt Pin Register ................................ 147
9.3.1.17 Offset 40h – HDCTL— Intel
®
High Definition Audio
β
Control
Register................................................................................. 147
9.3.1.18 Offset 4Ch – DCKCTL—Docking Control Register ......................... 147
9.3.1.19 Offset 4Dh – DCKSTS—Docking Status Register.......................... 148
9.3.1.20 Offset 50h: PM_CAPID - PCI Power Management Capability ID
Register................................................................................. 148
9.3.1.21 Offset 52h: PM_CAP – Power Management Capabilities Register .... 148
9.3.1.22 Offset 54h: PM_CTL_STS - Power Management Control And Status
Register................................................................................. 149
9.3.1.23 Offset 60h: MSI_CAPID - MSI Capability ID Register.................... 150
9.3.1.24 Offset 62h: MSI_CTL - MSI Message Control Register .................. 150
9.3.1.25 Offset 64h: MSI_ADR - MSI Message Address Register................. 150
9.3.1.26 Offset 68h: MSI_DATA - MSI Message Data Register ................... 150
9.3.1.27 Offset 70h: PCIE_CAPID – PCI Express* Capability Identifiers
Register................................................................................. 151