Datasheet

Memory Controller
Intel
®
Atom™ Processor E6xx Series Datasheet
69
6.0 Memory Controller
6.1 Overview
The Intel
®
Atom™ Processor E6xx Series contains an integrated 32-bit single-channel
memory controller that supports DDR2 memory in soldered down DRAM configurations
only. The memory controller supports data rates of 800 MT/s. There is no support for
ECC in the memory controller.
6.1.1 DRAM Frequencies and Data Rates
The memory controller supports the clock frequencies and data rates for DRAM listed in
Table 67.
6.2 DRAM Burst Length
The memory controller only supports a DRAM burst length of four 32-bit data chunks.
For 32-byte read/write transactions, the memory controller performs two back-to-back
16-byte DRAM transactions. For 64-byte read/write transactions, the memory
controller performs four back-to-back 16-byte DRAM transactions.
6.3 DRAM Partial Writes
The memory controller has support for partial writes to DRAM. There are four data
mask pins (M_DM[3:0]), one pin per byte used to indicate which bytes should be
written.
6.4 DRAM Power Management
Power Management involves managing and reducing the power consumed by both the
memory controller and the DRAM devices. The DRAM devices provide two ways to
reduce power consumption: Power Down mode and Self Refresh. The memory
controller manages these two power saving modes and, in addition, controls a number
of its own components to further reduce power consumption.
The memory controller supports memory power management in the following
conditions:
• C0–C1: Power Down
• C2–C6: Dynamic Self Refresh
•S3: Self Refresh
Table 67. Memory Controller Supported Frequencies and Data Rates
Memory Clock DRAM Clock DRAM Data Rate DRAM Type Peak Bandwidth
200 MHz 400 MHz 800 MT/s DDR2 3.2 GB/s