Datasheet

Register and Memory Mapping
Intel
®
Atom™ Processor E6xx Series Datasheet
67
5.5.3.8 Offset 3162h: D03IR – Device 3 Interrupt Route
5.5.4 General Configuration
5.5.4.1 Offset 3400h: RC – RTC Configuration
5.5.4.2 Offset 3410h: BNT– Boot Configuration
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Table 64. 3162h: D03IR – Device 3 Interrupt Route
Size: 16 bit Default: Power Well:
Memory Mapped IO BAR: RCBA Offset: 3162h
Bit Range Default Access Acronym Description
15 :12 3h RW IDR
Interrupt D Pin Route: Indicates which routing is used for INTD_B of
device 3
11 :08 2h RW ICR
Interrupt C Pin Route: Indicates which routing is used for INTC_B of
device 3
07 :04 1h RW IBR
Interrupt B Pin Route: Indicates which routing is used for INTB_B of
device 3
03 :00 0h RW IAR
Interrupt A Pin Route: Indicates which routing is used for INTA_B of
device 3
Table 65. 3400h: RC – RTC Configuration
Size: 32 bit Default: Power Well:
Memory Mapped IO BAR: RCBA Offset: 3400h
Bit Range Default Access Acronym Description
31 :03 0 RO RSVD Reserved
02 0 RWLO RSVD Reserved for future use
01 0 RWLO UL
Upper 128-byte Lock: When set, bytes 38h-3Fh in the upper 128-byte
bank of RTC RAM are locked. Writes will be dropped, and reads will not
return any guaranteed data.
00 0 RWLO LL
Lower 128-byte Lock: When set, bytes 38h-3Fh in the lower 128-byte
bank of RTC RAM are locked. Writes will be dropped, and reads will not
return any guaranteed data.
Table 66. 3410h: BNT– Boot Configuration
Size: 32 bit Default: Power Well:
Memory Mapped IO BAR: RCBA Offset: 3410h
Bit Range Default Access Acronym Description
31 :02 0 RO RSVD Reserved
01 0 RWO UL
Boot BIOS Strap Status:
1: Boot with the LPC interface
0: Boot from the SPI interface
00 0 RO RSVD Reserved