Datasheet

Register and Memory Mapping
Intel
®
Atom™ Processor E6xx Series Datasheet
64
5.5.2.8 Offset 3130h: D03IP – Device 3 Interrupt Pin
5.5.3 Interrupt Route Configuration
Indicates which interrupt routing is connected to the INTA/B/C/D pins reported in the
“DxIP” register fields. This will be the internal routing; the device interrupt is connected
to the interrupt controller.
5.5.3.1 Offset 3140h: D31IR – Device 31 Interrupt Route
Table 55. 3130h: D03IP – Device 3 Interrupt Pin
Size: 32 bit Default: Power Well:
Memory Mapped IO BAR: RCBA Offset: 3130h
Bit Range Default Access Acronym Description
31 :04 0 RO RSVD Reserved
03 :00 1h RW DP
Display Pin: Indicates which pin the graphics controller uses for
interrupts
Table 56. Interrupt Route Configuration
Bits Pin Bits Pin
0h PIRQA_B 4h PIRQE_B
1h PIRQB_B 5h PIRQF_B
2h PIRQC_B 6h PIRQG_B
3h PIRQD_B 7h PIRQH_B
8h-Fh Reserved
Table 57. 3140h: D31IR – Device 31 Interrupt Route
Size: 16 bit Default: Power Well:
Memory Mapped IO BAR: RCBA Offset: 3140h
Bit Range Default Access Acronym Description
15 :12 3h RW IDR
Interrupt D Pin Route: Indicates which routing is used for INTD_B of
device 31
11 :08 2h RW ICR
Interrupt C Pin Route: Indicates which routing is used for INTC_B of
device 31
07 :04 1h RW IBR
Interrupt B Pin Route: Indicates which routing is used for INTB_B of
device 31
03 :00 0h RW IAR
Interrupt A Pin Route: Indicates which routing is used for INTA_B of
device 31