Datasheet

Register and Memory Mapping
Intel
®
Atom™ Processor E6xx Series Datasheet
63
5.5.2.4 Offset 3120h: D26IP – Device 26 Interrupt Pin
5.5.2.5 Offset 3124h: D25IP – Device 25 Interrupt Pin
5.5.2.6 Offset 3128h: D24IP – Device 24 Interrupt Pin
5.5.2.7 Offset 312Ch: D23IP – Device 23 Interrupt Pin
Table 51. 3120h: D26IP – Device 26 Interrupt Pin
Size: 32 bit Default: Power Well:
Memory Mapped IO BAR: RCBA Offset: 3120h
Bit Range Default Access Acronym Description
31 :04 0 RO RSVD Reserved
03 :00 1h RW P4IP PCI Express* #4 Pin: Indicates which pin PCI Express* port #3 uses
Table 52. 3124h: D25IP – Device 25 Interrupt Pin
Size: 32 bit Default: Power Well:
Memory Mapped IO BAR: RCBA Offset: 3124h
Bit Range Default Access Acronym Description
31 :04 0 RO RSVD Reserved
03 :00 1h RW P3IP PCI Express* #3 Pin: Indicates which pin PCI Express* port #2 uses
Table 53. 3128h: D24IP – Device 24 Interrupt Pin
Size: 32 bit Default: Power Well:
Memory Mapped IO BAR: RCBA Offset: 3128h
Bit Range Default Access Acronym Description
31 :04 0 RO RSVD Reserved
03 :00 1h RW P2IP PCI Express* #2 Pin: Indicates which pin PCI Express* port #1 uses
Table 54. 312Ch: D23IP – Device 23 Interrupt Pin
Size: 32 bit Default: Power Well:
Memory Mapped IO BAR: RCBA Offset: 312Ch
Bit Range Default Access Acronym Description
31 :04 0 RO RSVD Reserved
03 :00 1h RW P1IP PCI Express* #1 Pin: Indicates which pin PCI Express* port #0 uses