Datasheet
Register and Memory Mapping
Intel
®
Atom™ Processor E6xx Series Datasheet
62
5.5.2 Interrupt Pin Configuration
The following registers tell each device which interrupt pint to report in the IPIN
register of their configuration space, as shown in Table 47.
5.5.2.1 Offset 3100h: D31IP – Device 31 Interrupt Pin
5.5.2.2 Offset 3110h: D27IP – Device 27 Interrupt Pin
5.5.2.3 Offset 3118h: D02IP – Device 2 Interrupt Pin
Table 47. Interrupt Pin Configuration
Bits Pin Bits Pin
0h No Interrupt 1h INTA_B
2h INTB_B 3h INTC_B
4h INTD_B 5h-Fh Reserved
Table 48. 3100h: D31IP – Device 31 Interrupt Pin
Size: 32 bit Default: Power Well:
Access
Memory Mapped IO BAR: RCBA Offset: 3100h
Bit Range Default Access Acronym Description
31 :04 0 RO RSVD Reserved
03 :00 0h RO LIP LPC Bridge Pin: The LPC bridge does not generate an interrupt.
Table 49. 3110h: D27IP – Device 27 Interrupt Pin
Size: 32 bit Default: Power Well:
Access
Memory Mapped IO BAR: RCBA Offset: 3110h
Bit Range Default Access Acronym Description
31 :04 0 RO RSVD Reserved
03 :00 1h RW HDAIP
Intel
®
HD Audio
β
Pin: Indicates which pin
the Intel
®
HD Audio
β
controller uses
Table 50. 3118h: D02IP – Device 2 Interrupt Pin
Size: 32 bit Default: Power Well:
Memory Mapped IO BAR: RCBA Offset: 3118h
Bit Range Default Access Acronym Description
31 :04 0 RO RSVD Reserved
03 :00 1h RW GP
Graphics Pin: Indicates which pin the graphics controller uses for
interrupts