Datasheet

Register and Memory Mapping
Intel
®
Atom™ Processor E6xx Series Datasheet
60
5.5 Bridging and Configuration
This describes all registers and base functionality that is related to chipset configuration
and not a specific interface. It contains the root complex register block. This block is
mapped into memory space, using RCBA. Accesses in this space are limited to 32-bit
quantities. Burst accesses are not allowed.
5.5.1 Root Complex Topology Capability Structure
The following registers follow the PCI Express* capability list structure as defined in the
PCI Express* specification, to indicate the capabilities of the component.
5.5.1.1 Offset 0000h: RCTCL – Root Complex Topology Capabilities List
Table 41. PCI Configuration Memory Bar Mapping
Field Configuration Cycle Bits Memory Cycle Bits
Bus Number 31:24 27:20
Device Number 23:19 19:15
Function Number 18:16 14:12
Register Number 11:02 11:02
Table 42. PCI Express* Capability List Structure
Start End Symbol Register Name
0000 0003 RCTCL Root Complex Topology Capability List
0004 0007 ESD Element Self Description
0010 0013 HDD Intel
®
High Definition Audio
β
Description (port 15)
0014 0017 Reserved Reserved
0018 008F HDBA Intel
®
High Definition Audio
β
Base Address (port 15)
Table 43. 0000h: RCTCL – Root Complex Topology Capabilities List
Size: 32 bit Default: Power Well:
Memory Mapped IO BAR: RCBA Offset: 0000h - 0003h
Bit Range Default Access Acronym Description
31 :20 000h RO NEXT Next Capability: Indicates the next item in the list
19 :16 1h RO CV Capability Version: Indicates the version of the capability structure
15 :00 0005h RO CID
Capability ID: Indicates that this is a PCI Express* link capability
section of an RCRB