Datasheet
Contents
Intel
®
Atom™ Processor E6xx Series Datasheet
6
7.7.2.8 Offset 14h: IOBAR - I/O Base Address .......................................106
7.7.2.9 Offset 2Ch: SS - Subsystem Identifiers ......................................106
7.7.2.10 Offset 34h: CAP_PTR - Capabilities Pointer..................................106
7.7.2.11 Offset 3Ch: INTR - Interrupt Information....................................106
7.7.2.12 Offset 58h: SSRW - Software Scratch Read Write ........................107
7.7.2.13 Offset 60h: HSRW - Hardware Scratch Read Write .......................107
7.7.2.14 Offset 90h: MID - Message Signaled Interrupts Capability.............107
7.7.2.15 Offset 92h: MC - Message Control .............................................107
7.7.2.16 Offset 94h: MA - Message Address.............................................108
7.7.2.17 Offset 98h: MD - Message Data.................................................108
7.7.2.18 Offset C4h: FD - Functional Disable ...........................................108
7.7.2.19 Offset E0h: SWSCISMI - Software SCI/SMI.................................109
7.7.2.20 Offset E4h: ASLE - System Display Event Register.......................109
7.7.2.21 Offset F0h: GCR - Graphics Clock Ratio ......................................109
7.7.2.22 Offset F4h: LBB - Legacy Backlight Brightness.............................110
8.0 PCI Express* .........................................................................................................111
8.1 Functional Description ......................................................................................111
8.1.1 Interrupt Generation .............................................................................111
8.1.2 Power Management...............................................................................111
8.1.2.1 Sleep State Support ................................................................111
8.1.2.2 Resuming from Suspended State...............................................111
8.1.2.3 Device Initiated PM_PME Message .............................................111
8.1.2.4 SMI/SCI Generation.................................................................112
8.1.3 Additional Clarifications .........................................................................112
8.1.3.1 Non-Snoop Cycles Are Not Supported ........................................112
8.2 PCI Express* Configuration Registers .................................................................112
8.2.1 PCI Type 1 Bridge Header ......................................................................112
8.2.1.1 VID — Vendor Identification......................................................113
8.2.1.2 DID — Device Identification......................................................113
8.2.1.3 CMD — PCI Command..............................................................114
8.2.1.4 PSTS — Primary Status............................................................114
8.2.1.5 RID — Revision Identification....................................................115
8.2.1.6 CC — Class Code.....................................................................115
8.2.1.7 CLS — Cache Line Size.............................................................116
8.2.1.8 HTYPE — Header Type .............................................................116
8.2.1.9 PBN — Primary Bus Number .....................................................116
8.2.1.10 SCBN — Secondary Bus Number ...............................................116
8.2.1.11 SBBN — Subordinate Bus Number .............................................117
8.2.1.12 IOBASE — I/O Base Address.....................................................117
8.2.1.13 IOLIMIT — I/O Limit Address ....................................................118
8.2.1.14 SSTS — Secondary Status........................................................118
8.2.1.15 MB — Memory Base Address.....................................................119
8.2.1.16 ML — Memory Limit Address.....................................................119
8.2.1.17 PMB — Prefetchable Memory Base Address .................................119
8.2.1.18 PML — Prefetchable Memory Limit Address .................................120
8.2.1.19 CAPP — Capabilities Pointer......................................................120
8.2.1.20 ILINE — Interrupt Line.............................................................120
8.2.1.21 IPIN — Interrupt Pin................................................................121
8.2.1.22 BCTRL — Bridge Control...........................................................121
8.2.2 Root Port Capability Structure ................................................................122
8.2.2.1 CLIST — Capabilities List..........................................................123
8.2.2.2 XCAP — PCI Express* Capabilities .............................................123
8.2.2.3 DCAP — Device Capabilities ......................................................123
8.2.2.4 DCTL — Device Control ............................................................124
8.2.2.5 DSTS — Device Status.............................................................125
8.2.2.6 LCAP — Link Capabilities ..........................................................125
8.2.2.7 LCTL — Link Control ................................................................126
8.2.2.8 LSTS — Link Status .................................................................126