Datasheet

Intel

Atom™ Processor E6xx Series Datasheet

5.4.1.2 IO BAR

The Intel

Atom™ Processor E6xx Series uses a programmable base address (BAR) to

set a range of IO locations that it will use to decode PORT IN and/or PORT OUT from the

CPU and directly accesses a register(s). The BAR register is generally located in the PCI

configuration space and is programmable by the BIOS/OS.

5.4.1.3 Hard-Coded Memory Access

The Intel

Atom™ Processor E6xx Series decodes CPU memory reads/writes to

memory locations not covered by system DRAM. These locations are unmovable.

5.4.1.4 Memory BAR

The Intel

Atom™ Processor E6xx Series uses a programmable base address (BAR) to

set a range of memory locations that it will use to decode CPU memory reads/writes (to

memory locations not covered by system DRAM) and directly accesses a register(s).

The BAR register is generally located in PCI configuration space and is programmable

by the BIOS/OS.

5.4.2 Indirect Register Access

5.4.2.1 PCI Config Space

Each PCI device (as defined in Table 39) has a standard PCI header defined consisting

of 256 bytes. Access to PCI configuration space is through two methods: I/O indexed

and memory mapped.

5.4.2.1.1 PCI Configuration Access - I/O Indexed Scheme

Accesses to configuration space may be performed via the hard-coded DWORD I/O

ports CF8h and CFCh. In this mode, software uses CF8h as an index register, indicating

which configuration space to access, and CFCh as the data register. Accesses to CF8h

will be captured internally and stored. Upon a read or write access to CFCh, a

configuration cycle will be generated with the address specified from the data stored in

CF8h. The format of the address is as shown in Table 40.

Note: Bit 31 of offset CF8h must be set for a configuration cycle to be generated.

5.4.2.1.2 PCI Config Access - Memory Mapped Scheme

A flat, 256 MB memory space may also be allocated to perform configuration

transactions. This is enabled through a special register on the message network. This

sets a 4-bit base which is compared against bits 31:28 of the incoming memory

address. If these four bits match, the cycle is turned into a configuration cycle with the

fields shown in Table 41.

Table 40. PCI Configuration PORT CF8h Mapping

Field Configuration Cycle Bits I/O CF8h Cycle Bits

Bus Number 31:24 23:16

Device Number 23:19 15:11

Function Number 18:16 10:08