Datasheet
Register and Memory Mapping
Intel
®
Atom™ Processor E6xx Series Datasheet
57
5.3.1.2 Variable I/O Address Range
Table 38 shows the variable I/O decode ranges. They are set using base address
registers (BARs) or other configuration bits in various configuration spaces. The PnP
software (PCI or ACPI) can use their configuration mechanisms to set and adjust these
values.
Warning: The variable I/O ranges should not be set to conflict with the fixed I/O ranges. There
will be unpredictable results if the configuration software allows conflicts to occur. The
Intel
®
Atom™ Processor E6xx Series does not check for conflicts.
5.3.2 PCI Devices and Functions
The Intel
®
Atom™ Processor E6xx Series incorporates a variety of PCI devices and
functions, as shown in Table 39.
74h RTC NMI and RTC No
75h RTC RTC No
76h RTC NMI and RTC No
77h RTC RTC No
84h-86h Internal Internal No
88h Internal Internal No
8Ch-8Eh Internal Internal No
A0h-ACh 8259 Slave 8259 Slave No
B0h 8259 Slave 8259 Slave No
B2h-B3h Power Management Power Management No
B4h-BCh 8259 Slave 8259 Slave No
3B0h-3BBh VGA VGA Yes
3C0h-3DFh VGA VGA Yes
CF8h, CFCh Internal Internal No
CF9h Reset Generator Reset Generator No
Table 37. Fixed I/O Range Decoded by the Processor (Sheet 2 of 2)
I/O Address Read Target Write Target Can be disabled?
Table 38. Variable I/O Range Decoded by the Processor
Range Name Mappable Size (bytes) Target
ACPI P_BLK Anywhere in 64k I/O space 16 Power Management
SMBus Anywhere in 64k I/O space 32 SMB Unit
GPIO Anywhere in 64k I/O space 64 GPIO
Table 39. PCI Devices and Functions (Sheet 1 of 2)
Bus: Device: Function # Functional Description
Bus 0: Device 0: Function 0 Host Bridge
Bus 0: Device 2: Function 0 Integrated Graphics and Video Device
Bus 0: Device 3: Function 0 SDVO Display Unit
Bus 0: Device 23: Function 0 PCI Express* Port 0
Bus 0: Device 24: Function 0 PCI Express* Port 1