Datasheet

Register and Memory Mapping
Intel
®
Atom™ Processor E6xx Series Datasheet
54
• Control registers are I/O mapped into the processor I/O space that controls access
to PCI and PCI Express* configuration space.
• Internal configuration registers residing within the processor are partitioned into
nine logical device register sets, one for each PCI device listed in Table 39. (These
are “logical” devices because they reside within a single physical device.)
The processor’s internal registers (I/O Mapped, Configuration and PCI Express*
Extended Configuration registers) are accessible by the host processor. The registers
that reside within the lower 256 bytes of each device can be accessed as Byte, Word
(16-bit), or DWord (32-bit) quantities, with the exception of CONFIG_ADDRESS, which
can only be accessed as a DWord. All multi-byte numeric fields use little-endian
ordering (i.e., lower addresses contain the least significant parts of the field). Registers
which reside in bytes 256 through 4095 of each device may only be accessed using
memory mapped transactions in DWord (32-bit) quantities. Some of the registers
described in this section contain reserved bits. These bits are labeled Reserved.
Software must deal correctly with fields that are reserved. On reads, software must use
appropriate masks to extract the defined bits and not rely on reserved bits being any
particular value. On writes, software must ensure that the values of reserved bit
positions are preserved. That is, the values of reserved bit positions must first be read,
merged with the new values for other bit positions and then written back.
Note: Software does not need to perform read, merge, and write operations for the
configuration address register.
Software must not generate configuration requests from memory-mapped accesses
that cross DWORD boundary, as this will result in unpredictable behavior.
In addition to reserved bits within a register, the processor contains address locations
in the configuration space of the Host Bridge entity that are marked either Reserved or
Intel Reserved. The processor responds to accesses to Reserved address locations by
completing the host cycle. When a Reserved register location is read, a zero value is
returned. (Reserved registers can be 8, 16, or 32 bits in size). Writes to Reserved
registers have no effect on the processor. Registers that are marked as Intel Reserved
must not be modified by system software. Writes to Intel Reserved registers may cause
system failure. Reads from Intel Reserved registers may return a non-zero value.
Upon a Cold Reset, the processor sets all configuration registers to predetermined
default states. Some default register values are determined by external strapping
options. The default state represents the minimum functionality feature set required to
successfully bring up the system; it does not represent the optimal system
configuration. It is the responsibility of the system initialization software (usually BIOS)
to properly determine the DRAM configurations and to program the system memory
accordingly.
5.3 System Memory Map
The Intel
®
Atom™ Processor E6xx Series supports up to 2 GB of physical DDR2
memory space and 64 kB + 3 of addressable I/O space. There is a programmable
memory address space under the 1 MB region which is divided into regions that can be
individually controlled with programmable attributes such as Disable, Read/Write, Write
Only, or Read Only. This section describes how the memory space is partitioned and
how those partitions are used.
Top of Memory (TOM) is the highest address of physical memory actually installed in
the system. A TOM of greater than 2 GB is not supported. Memory addresses above 2
GB will be routed to internal controllers or external I/O devices.
Figure 3 represents the system memory address map in a simplified form.