Datasheet
Contents
Intel
®
Atom™ Processor E6xx Series Datasheet
5
6.3 DRAM Partial Writes........................................................................................... 69
6.4 DRAM Power Management.................................................................................. 69
6.4.1 Powerdown Modes.................................................................................. 70
6.4.2 Self Refresh Mode .................................................................................. 70
6.4.3 Dynamic Self Refresh Mode ..................................................................... 70
6.4.4 Page Management..................................................................................70
6.5 Refresh Mode.................................................................................................... 70
6.6 Supported DRAM Configurations.......................................................................... 71
6.7 Supported DRAM Devices ................................................................................... 72
6.8 Supported Rank Configurations ...........................................................................72
6.9 Address Mapping and Decoding...........................................................................73
7.0 Graphics, Video, and Display ................................................................................... 75
7.1 Chapter Contents ..............................................................................................75
7.2 Overview .........................................................................................................75
7.2.1 3D Graphics ..........................................................................................75
7.2.2 Shading Engine Key Features...................................................................76
7.2.3 Vertex Processing................................................................................... 77
7.2.3.1 Vertex Transform Stages ........................................................... 77
7.2.3.2 Lighting Stages ........................................................................77
7.2.4 Pixel Processing ..................................................................................... 78
7.2.4.1 Hidden Surface Removal............................................................ 78
7.2.4.2 Applying Textures and Shading................................................... 78
7.2.4.3 Final Pixel Formatting................................................................ 78
7.2.5 Unified Shader....................................................................................... 78
7.2.6 Multi Level Cache ...................................................................................79
7.3 Video Encode.................................................................................................... 79
7.3.1 Supported Input Formats ........................................................................79
7.3.1.1 Encoding Pipeline...................................................................... 79
7.3.1.2 Encode Codec Support...............................................................80
7.3.1.3 Encode Specifications Supported................................................. 80
7.4 Video Decode ................................................................................................... 81
7.4.1 Entropy Coding ......................................................................................81
7.4.1.1 Motion Compensation................................................................ 82
7.4.1.2 Deblocking............................................................................... 82
7.4.1.3 Output Reference Frame Storage Format ..................................... 82
7.4.1.4 Pixel Format............................................................................. 83
7.5 Display ........................................................................................................... 83
7.5.1 Display Output Stages ............................................................................ 85
7.5.1.1 Planes..................................................................................... 85
7.5.1.2 Display Pipes............................................................................ 86
7.5.2 Display Ports ......................................................................................... 86
7.5.2.1 LVDS Port................................................................................ 87
7.5.2.2 LVDS Backlight Control.............................................................. 88
7.5.2.3 SDVO Digital Display Port .......................................................... 88
7.5.2.4 SDVO DVI/HDMI.......................................................................89
7.6 Control Bus ...................................................................................................... 89
7.7 Configuration Registers ...................................................................................... 90
7.7.1 D2:F0 PCI Configuration Registers............................................................90
7.7.2 D3:F0 PCI Configuration Registers.......................................................... 102
7.7.2.1 Offset 00h: ID – Identifiers ...................................................... 103
7.7.2.2 Offset 04h: CMD – PCI Command ............................................. 103
7.7.2.3 Offset 06h: STS - PCI Status.................................................... 104
7.7.2.4 Offset 08h: RID - Revision Identification .................................... 104
7.7.2.5 Offset 09h: CC - Class Codes.................................................... 104
7.7.2.6 Offset 0Eh: HDR - Header Type ................................................ 105
7.7.2.7 Offset 10h: MMADR - Memory Mapped Base Address ................... 105