Datasheet

Signal Description
Intel
®
Atom™ Processor E6xx Series Datasheet
42
2.12 General Purpose I/O
2.13 Functional Straps
The following signals are used to configure certain processor features.
THRM_B
I
CMOS3.3
Core
Thermal Alarm: Generated by external hardware to
generate SMI_B/SCI.
CRU/PLL
HPLL_REFCLK_P
HPLL_REFCLK_N
I
CMOS
Core Reference clock: Host PLL CLK Differential pair: 100 MHz.
Table 16. General Purpose I/O Signals
Signal Name Type
Power
Well
Description
GPIO_SUS[8:0]
I/O
CMOS3.3
SUS
General Purpose IO: These signals are powered off of the
suspend well power plane within the processor. They are
accessible during the S3 sleep state. GPIO_SUS[7] can be
used to wake the system from Suspend-to-RAM while
GPIO_SUS[1:4] can be used to wake the system from
Suspend-to-RAM, provided LVDS is disabled on the platform.
GPIO_SUS[7] is required to strap to 1 during platform
boot up for Intel
®
Atom™ Processor E6xx Series B-1
Stepping.
GPIO[4:0]
I/O
CMOS3.3
Core
General Purpose IO: These signals are powered off of the
core well power plane within the processor.
Table 15. Miscellaneous Signals and Clocks (Sheet 4 of 4)
Signal Name
Direction/
Type
Power
Well
Description
Table 17. Functional Straps (Sheet 1 of 2)
Signal Name Strap Definition
GPIO_SUS[0]
STRAP_MEM_DEV_WIDTH: Defines the memory device width.
0: x16 devices
1: x8 devices
GPIO_SUS[6:5]
STRAP_MEM_DEV[1:0] = GPIO_SUS[6:5].
Defines the memory device densities connected.
11: 2 Gb
10: 1 Gb
01: 512 Mb
00: 256 Mb
GPIO_SUS[8]
STRAP_MEM_RANK: Defines the number of ranks enabled.
1: 1 Rank
0: 2 Rank