Datasheet
Signal Description
Intel
®
Atom™ Processor E6xx Series Datasheet
41
VIDEN[1:0]
O
CMOS
Core
Voltage ID Enable: Indicates which voltage is being
specified on the VID pins:
00: VID is Invalid
01: VID = Vcc
10: VID = Vnn
11: Unused
TEST_B
I
CMOS3.3
SUS
TEST: When asserted, component is put into TEST modes
combinatorially.
RCOMP
I
A
Core Connect 249 Ω resistor to 1.05 V
IOCMREF
I/O
A
Core
CMOS VREF
1 kΩ ± 1% pullup to V1P05_S and 1 kΩ ± 1% pull-down to
GND
IOCOMP1[1:0]
I/O
A
Core
IOCOMP1[0] externally connects to 18.2 Ω resistor 1% to Vss
IOCOMP1[1] externally connects to 35.7 Ω resistor 1% to Vss
IOCOMP0[1:0]
I/O
A
Core
IOCOMP0[0] externally connects to 27.4 Ω resistor 1% to Vss
IOCOMP0[1] externally connects to 54.9 Ω resistor 1% to Vss
IO_RX_CVREF
I/O
A
Core
CMOS VREF
510 Ω ± 5% pullup to V1P05_S and 1 kΩ ± 1% pull-down to
GND
IO_RX_GVREF
I/O
A
Core
GTL VREF
510 Ω ± 5% pullup to V1P05_S and 1 kΩ ± 1% pull-down to
GND
DLIOCMREF
I
Power
Core
Connect to VCCP
1 kΩ ± 1% pullup to V1P05_S and 2 kΩ ± 1% pull-down to
GND
IOGTLREF
I/O
A
Core
GTL VREF
1 kΩ ± 1% pullup to V1P05_S and 1 kΩ ± 1% pull-down to
GND
DLIOGTLREF
I
Power
Core
Connect to VCCP
1 kΩ ± 1% pullup to V1P05_S and 2 kΩ ± 1% pull-down to
GND
VNNSENSE
VCC_VSSSENSE
VCCSENSE
I
A
Core
Voltage sense: Connects to Intel
®
MVP-6. Voltage
Regulator must connect feedback lines for VCC, VSS
and VNN to these pins on the package.
Thermal
THRMDA
I
A
Passiv
e
Thermal Diode - Anode
THRMDC
O
A
Passiv
e
Thermal Diode - Cathode
CLK14
I
CMOS3.3
Core
Oscillator Clock: This signal is used for 8254 timers and
HPET. It runs at 14.31818 MHz. This clock stops (and should
be low) during S3, S4, and S5 states. CLK14 must be
accurate to within 500 ppm over 100 us (and longer periods)
to meet HPET accuracy requirements.
SPKR
O
CMOS3.3
Core
Speaker: The SPKR signal is the output of counter 2 and is
internally ANDed with Port 61h bit 1 to provide Speaker Data
Enable. This signal drives an external speaker driver device,
which in turn drives the system speaker. Upon SLPMODE, its
output state is 0.
SMI_B
I
CMOS3.3
Core
System Management Interrupt: This signal is generated
by the external system management controller.
Table 15. Miscellaneous Signals and Clocks (Sheet 3 of 4)
Signal Name
Direction/
Type
Power
Well
Description