Datasheet
Signal Description
Intel
®
Atom™ Processor E6xx Series Datasheet
40
GPIO_B
I/O
AGTL+
Core
General Purpose I/O / External Thermal Sensor: Same
pin type as BPM[]. GPIO in this case is NOT the ACPI notion
with lots of software configurability. Instead, this is
essentially a spare pin that can be configured as a input or
output which the microcontroller can respond to. It can also
be configured as an external thermal sensor input.
THERMTRIP_B
I/O
OD
Core
Catastrophic Thermal Trip: The processor has reached an
operating temperature that may damage the part. Platform
should immediately cut power to the processor.
THERMTRIP_B is not valid in M0, M2, and M3 PWRMODE
states.
GTLVREF
I
A
Core
Voltage Reference for GPIO_B. 2/3 Vccp via external
voltage divider: 1 kΩ to Vccp, 2 KΩ to vss.
BSEL[0]/IERR
O
CMOS
Core
Reference Frequency Select / Internal Error: Depending
on PowerMode[2:0]:
BSEL: Combined with BSEL[1] and BSEL[2], Selects External
Reference Clock and DDR frequencies.
000 - SKU_100 (DDR: 800)
001 - Reserved
010 - Reserved
011 - Reserved
100 - Reserved
101 - Reserved
110 - Reserved
110 – Reserved
IERR: Internal Error indication (debug). Positively asserted.
Asserted when CPU has had an internal error and may have
unexpectedly stopped executing. Assertion of IERR is usually
accompanied by a SHUTDOWN transaction internal to the
processor which may result in assertion of NMI to the CPU.
The processor will keep IERR asserted until the
POWERMODE[] pins take the processor to reset.
BSEL[2:1]
O
CMOS
Core
Bus Frequency Select: Like BSEL[0]/IERR, this pin reflects
the processor External Reference Clock and DDR2 frequency.
PWRMODE[2:0]
I
CMOS
Core
Power Mode: System management controller is expected to
sequence the processor through various states using the
POWERMODE[] pins to facilitate cold reset and warm reset.
BCLKP/BLCKN
I
Diff
Core Reference Clock: Differential - 100 MHz.
VID[6:0]
I/O
CMOS
Core
Voltage ID: Indicates a desired voltage for either VCC or the
VNN depending on the VIDEN pins. Resolution of 12.5 mV
according to the Intel
®
MVP-6 spec.
Table 15. Miscellaneous Signals and Clocks (Sheet 2 of 4)
Signal Name
Direction/
Type
Power
Well
Description
PowerMode[2:0] BSEL/IERR Select
M0 INVALID
M2 INVALID -> BSEL
M3, M1 BSEL
M5 IERR
M7, M6, M4 Undef