Datasheet
Contents
Intel
®
Atom™ Processor E6xx Series Datasheet
4
3.8 SPI Interface Signals..........................................................................................48
3.9 Power Management Interface Signals ...................................................................48
3.10 Real Time Clock Interface Signals ........................................................................49
3.11 JTAG and Debug Interface ..................................................................................49
3.12 Miscellaneous Signals and Clocks .........................................................................49
3.13 General Purpose I/O...........................................................................................50
3.14 Integrated Termination Resistors .........................................................................50
4.0 System Clock Domains .............................................................................................51
5.0 Register and Memory Mapping.................................................................................53
5.1 Address Map .....................................................................................................53
5.2 Introduction......................................................................................................53
5.3 System Memory Map..........................................................................................54
5.3.1 I/O Map.................................................................................................56
5.3.1.1 Fixed I/O Address Range............................................................56
5.3.1.2 Variable I/O Address Range........................................................57
5.3.2 PCI Devices and Functions .......................................................................57
5.4 Register Access Method ......................................................................................58
5.4.1 Direct Register Access.............................................................................58
5.4.1.1 Hard Coded IO Access................................................................58
5.4.1.2 IO BAR ....................................................................................59
5.4.1.3 Hard-Coded Memory Access........................................................59
5.4.1.4 Memory BAR.............................................................................59
5.4.2 Indirect Register Access...........................................................................59
5.4.2.1 PCI Config Space.......................................................................59
5.5 Bridging and Configuration..................................................................................60
5.5.1 Root Complex Topology Capability Structure...............................................60
5.5.1.1 Offset 0000h: RCTCL – Root Complex Topology Capabilities List ......60
5.5.1.2 Offset 0004h: ESD – Element Self Description...............................61
5.5.1.3 Offset 0010h: HDD – Intel
®
High Definition Audio
β
Description........61
5.5.1.4 Offset 0018h: HDBA – Intel
®
High Definition Audio
β
Base Address ...61
5.5.2 Interrupt Pin Configuration.......................................................................62
5.5.2.1 Offset 3100h: D31IP – Device 31 Interrupt Pin..............................62
5.5.2.2 Offset 3110h: D27IP – Device 27 Interrupt Pin..............................62
5.5.2.3 Offset 3118h: D02IP – Device 2 Interrupt Pin................................62
5.5.2.4 Offset 3120h: D26IP – Device 26 Interrupt Pin..............................63
5.5.2.5 Offset 3124h: D25IP – Device 25 Interrupt Pin..............................63
5.5.2.6 Offset 3128h: D24IP – Device 24 Interrupt Pin..............................63
5.5.2.7 Offset 312Ch: D23IP – Device 23 Interrupt Pin..............................63
5.5.2.8 Offset 3130h: D03IP – Device 3 Interrupt Pin................................64
5.5.3 Interrupt Route Configuration...................................................................64
5.5.3.1 Offset 3140h: D31IR – Device 31 Interrupt Route..........................64
5.5.3.2 Offset 3148h: D27IR – Device 27 Interrupt Route..........................65
5.5.3.3 Offset 314Ah: D26IR – Device 26 Interrupt Route..........................65
5.5.3.4 Offset 314Ch: D25IR – Device 25 Interrupt Route .........................65
5.5.3.5 Offset 314Eh: D24IR – Device 24 Interrupt Route..........................66
5.5.3.6 Offset 3150h: D23IR – Device 23 Interrupt Route..........................66
5.5.3.7 Offset 3160h: D02IR – Device 2 Interrupt Route ...........................66
5.5.3.8 Offset 3162h: D03IR – Device 3 Interrupt Route ...........................67
5.5.4 General Configuration..............................................................................67
5.5.4.1 Offset 3400h: RC – RTC Configuration..........................................67
5.5.4.2 Offset 3410h: BNT– Boot Configuration........................................67
6.0 Memory Controller ...................................................................................................69
6.1 Overview..........................................................................................................69
6.1.1 DRAM Frequencies and Data Rates............................................................69
6.2 DRAM Burst Length............................................................................................69