Datasheet

Signal Description
Intel
®
Atom™ Processor E6xx Series Datasheet
39
2.11 Miscellaneous Signals and Clocks
Table 15. Miscellaneous Signals and Clocks (Sheet 1 of 4)
Signal Name
Direction/
Type
Power
Well
Description
Legacy (North Complex)
CMREF
I
Power
Core
Non-Strobe Signals’ Reference Voltage for DMI:
Externally set via passive voltage divider.
1KΩ to Vccp. 1 KΩ to Vss.
GTLREF
I
Power
Core
Strobe Signals’ Reference Voltage for DMI: Externally
set via passive voltage divider.
1KΩ to Vccp. 1 KΩ to Vss.
COMP0[1:0]
I
A
Core
RCOMP: Connected to high-precision resistors on the
motherboard. Used for compensating DMI pull-up / pull-down
impedances.
COMP0[0] externally connects to 27.4 Ω 1% to Vss
COMP0[1] externally connects to 54.9 Ω 1% to Vss
COMP1[1:0]
I
A
Core
RCOMP: Connected to high-precision resistors on the
motherboard. Used for compensating pull-up / pull-down
impedances.
COMP1[0] externally connects to 18.2 Ω 1% to Vss.
COMP1[1] externally connects to 35.7 Ω 1% to Vss.
BPM_B[3:0]
I/O
AGTL+
Core
Break/Perf Monitor: Various debug input and output
functions.
NCTDO
O
OD
Core
North TAP TDO: If the CPU TAP selects NCTAP mode, this
pin is used as TDO output for the NCTAP. When NCTAP is not
enabled, this pin is undef.
When used as NCTAP TDO, requires external 56 Ω pullup to
vccp (open drain).
NCTDI
I
CMOS
Core
North Complex JTAG Test Data Input: Transfers serial
test data into the processor. TDI provides the serial input
needed for JTAG specification support.
NCTCK
I
CMOS
Core
NCTAP TCLK or Low Yield Analysis (Negative): If the
CPU TAP selects NCTAP mode, this pin is used as TCLK input
for the NCTAP. Otherwise, this pin is used for testing of CPU’s
L2 cache. When used as NCTAP TCLK, requires external 56 Ω
resistor to Vss
NCTMS
I
CMOS
Core
NCTAP TMS or Low Yield Analysis (Positive): If the CPU
TAP selects NCTAP mode, this pin is used as TMS input for the
NCTAP. Otherwise, this pin is used for testing of CPU’s L2
cache.
When used as NCTAP TMS, requires external 56 Ω pullup to
vccp.
PRDY_B
I/O
AGTL+
Core
Probe Mode Ready: CPU is response to PREQ_B assertion.
Indicates CPU is in probe mode. Input unused.
PREQ_B
I/O
AGTL+
Core
Probe Mode Request: Assertion is a Request for the CPU to
enter probe mode. CPU will response with PRDY_B assertion
once it has entered. PREQ_B can be enabled to cause the
CPU to break from C4 and C6.
GTLPREF
I/O
Power
Core
Voltage Reference for GPIO_B. 2/3 Vccp via external
voltage divider: 1 kΩ to Vccp, 2 KΩ to VSS.
PROCHOT_B
I/O
I:CMOS
O:OD
Core
Processor Hot: CPU and optionally GMCH drives when it is
throttling due to temperature. Can also be an input which
causes the CPU and optional GMCH to throttle.
External 22.1 ± 1% Ω resistor in series with 60.4 ± 1% Ω
pull-up to Vccp.