Datasheet

Signal Description
Intel
®
Atom™ Processor E6xx Series Datasheet
38
2.9 Real Time Clock Interface Signals
2.10 JTAG and Debug Interface
The JTAG interface is accessible only after PWROK is asserted.
Table 13. Real Time Clock Interface Signals
Signal Name
Direction/
Type
Power
Well
Description
RTCX1
Special
A
RTC
Crystal Input 1: This signal is connected to the 32.768-kHz
crystal. If no external crystal is used, then RTCX1 can be
driven with the desired clock rate.
RTCX2
Special
A
RTC
Crystal Output 2: This signal is connected to the 32.768-
kHz crystal. If no external crystal is used, then RTCX2 should
be left floating.
VCCRTCEXT
I
Power
RTC External capacitor connection
Table 14. JTAG and Debug Interface Signals
Signal Name
Direction/
Type
Power
Well
Description
TCK
I
CMOS
Core
CPU JTAG Test Clock: Provides the clock input for the
processor Test Bus (also known as the Test Access Port).
TDI
I
CMOS
Core
CPU JTAG Test Data Input: Transfers serial test data into
the processor. TDI provides the serial input needed for JTAG
specification support.
TDO
O
CMOS_OD
Core
CPU JTAG Test Data Output: Transfers serial test data out
of the processor. TDO provides the serial output needed for
JTAG specification support.
TMS
I
CMOS
Core
CPU JTAG Test Mode Select: A JTAG specification support
signal used by debug tools.
TRST_B
I
CMOS
Core
CPU JTAG Test Reset: Asynchronously resets the Test
Access Port (TAP) logic. TRST_B must be driven asserted
(low) during CPU power on Reset.
IO_TDI
I
CMOS
Core
JTAG Test Data In: TDI is used to serially shift data and
instructions into the TAP.
IO_TDO
O
CMOS_OD
Core
JTAG Test Data Out: TDO is used to serially shift data out
of the device.
IO_TMS
I
CMOS
Core
JTAG Test Mode Select: This signal is used to control the
state of the TAP controller.
IO_TCK
I
CMOS
Core JTAG Test Clock: Provides the clock input for TAP controller.
IO_TRST_B
I
CMOS
Core
JTAG Test Reset: Asynchronously resets the Test Access
Port (TAP) logic. IO_TRST_B must be driven asserted (low)
during power on Reset.