Datasheet

Signal Description
Intel
®
Atom™ Processor E6xx Series Datasheet
36
2.5 LPC Interface Signals
Note: Boot from LPC is not supported.
2.6 SMBus Interface Signals
2.7 SPI Interface Signals
Table 9. LPC Interface Signals
Signal Name
Direction/
Type
Power
Well
Description
LPC_AD[3:0]
I/O
CMOS3.3
Core LPC Address/Data: Multiplexed Command, Address, Data
LPC_FRAME_B
O
CMOS3.3
Core LPC Frame: This signal indicates the start of an LPC cycle.
LPC_SERIRQ
I/O
CMOS3.3
Core
Serial Interrupt Request: This signal conveys the serial
interrupt protocol.
LPC_CLKRUN_B
I/O
CMOS3.3
Core
Clock Run: This signal gates the operation of the
LPC_CLKOUTx. Once an interrupt sequence has started,
LPC_CLKRUN_B should remain asserted to allow the
LPC_CLKOUTx to run.
LPC_CLKOUT[2:0]
O
CMOS3.3
Core
LPC Clock: These signals are the clocks driven by the
processor to LPC devices. Each clock can support up to two
loads.
Note: The primary boot device like SPI (behind SMC)
should be connected to LPC_CLKOUT[0]
Table 10. SMBus Interface Signals
Signal Name
Direction/
Type
Power
Well
Description
SMB_DATA
I/O
CMOS3.3_OD
Core
SMBus Data: This signal is the SMBus data pin. An external
pull-up resistor is required.
SMB_CLK
I/O
CMOS3.3_OD
Core
SMBus Clock: This signal is the SMBus clock pin. An external
pull-up resistor is required.
SMB_ALERT_B
I
CMOS3.3
Core
SMBus Alert: This signal can be used to generate an
interrupt, or generate an SMI_B.
Table 11. SPI Interface Signals
Signal Name
Direction/
Type
Power
Well
Description
SPI_MOSI
O
CMOS3.3
Core SPI Data Output: Unidirectional output data for the SPI IF.
SPI_MISO
I
CMOS3.3
Core SPI Data Input: Unidirectional input data for the SPI IF.
SPI_CS_B
O
CMOS3.3
Core
SPI Chip Select Signal: When asserted low, the SPI
peripheral is selected.
SPI_SCK
O
CMOS3.3
Core SPI Clock Output: Serial clock accompanying data.