Datasheet

Signal Description
Intel
®
Atom™ Processor E6xx Series Datasheet
34
2.2.2 Serial Digital Video Output (SDVO) Signals
Table 6. Serial Digital Video Output Signals
Signal Name Direction/Type
Power
Well
Description
SDVO_REDP
SDVO_REDN
O
PCIe*
Core
Serial Digital Video Red: SDVO_RED[±] is a differential
data pair that provides red pixel data for the SDVO channel
during Active periods. During blanking periods it may provide
additional such as sync information, auxiliary configuration
data, etc. This data pair must be sampled with respect to the
SDVO_CLK[±] signal pair.
SDVO_GREENP
SDVO_GREENN
O
PCIe*
Core
Serial Digital Video Green: SDVO_GREEN[±] is a
differential data pair that provides green pixel data for the
SDVO channel during Active periods. During blanking periods
it may provide additional such as sync information, auxiliary
configuration data, etc. This data pair must be sampled with
respect to the SDVO_CLK[±] signal pair.
SDVO_BLUEP
SDVO_BLUEN
O
PCIe*
Core
Serial Digital Video Blue: SDVO_BLUE[±] is a differential
data pair that provides blue pixel data for the SDVO channel
during Active periods. During blanking periods it may provide
additional such as sync information, auxiliary configuration
data, etc. This data pair must be sampled with respect to the
SDVO_CLK[±] signal pair.
SDVO_CLKP
SDVO_CLKN
O
PCIe*
Core
Serial Digital Video Clock: This differential clock signal pair
is generated by the internal PLL and runs between 100 MHz
and 200 MHz.
If TV-out mode is used, the SDVO_TVCLKIN[±] clock input is
used as the frequency reference for the PLL. The
SDVO_CLK[±] output pair is then driven back to the SDVO
device.
SDVO_INTP
SDVO_INTN
I
PCIe*
Core
Serial Digital Video Input Interrupt: Differential input
pair that may be used as an interrupt notification from the
SDVO device. This signal pair can be used to monitor hot
plug attach/detach notifications for a monitor driven by an
SDVO device.
SDVO_TVCLKINP
SDVO_TVCLKINN
I
PCIe*
Core
Serial Digital Video TV-OUT Synchronization Clock:
Differential clock pair that is driven by the SDVO device. If
SDVO_TVCLKIN[±] is used, it becomes the frequency
reference for the dot clock PLL, but will be driven back to the
SDVO device through the SDVO_CLK[±] differential pair.
This signal pair has an operating range of 100–200 MHz, so if
the desired display frequency is less than 100 MHz, the SDVO
device must apply a multiplier to get the SDVO_TVCLKIN[±]
frequency into the 100- to 200-MHz range.
SDVO_STALLP
SDVO_STALLN
I
PCIe*
Core
Serial Digital Video Field Stall: Differential input pair that
allows a scaling SDVO device to stall the pixel pipeline.
SDVO_CTRLCLK
I/O
CMOS3.3_OD
Core
SDVO Control Clock: Single-ended control clock line to the
SDVO device. Similar to I
2
C* clock functionality, but may run
at faster frequencies. SDVO_CTRLCLK is used in conjunction
with SDVO_CTRLDATA to transfer device config, PROM, and
monitor DDC information. This interface directly connects to
the SDVO device.
SDVO_CTRLDATA
I/O
CMOS3.3_OD
Core
SDVO Control Data: SDVO_CTRLDATA is used in
conjunction with SDVO_CTRLCLK to transfer device config,
PROM, and monitor DDC information. This interface directly
connects to the SDVO device.
SDVO_REFCLKP
SDVO_REFCLKN
I
SDVO
Core
SDVO Reference Clock: Display PLL Positive/Negative Ref
Clock