Datasheet

Signal Description
Intel
®
Atom™ Processor E6xx Series Datasheet
32
2.1 System Memory Signals
Table 4. System Memory Signals
Signal Direction/Type Power Well Description
M_ODT[1:0]
O
CMOS1.8
Core
On-Die Termination Enable: (active high) One pin per
rank (2 ranks supported)
M_CKP
O
CMOS1.8
Core
Differential DDR Clock: The crossing of the positive edge
of M_CKP and the negative edge of M_CKN is used to
sample the address and control signals on memory.
M_CKN
O
CMOS1.8
Core Complementary Differential DDR Clock
M_CKE[1:0]
O
CMOS1.8
SUS
Clock Enable: (active high) M_CKE is used for power
control of the DRAM devices. There is one M_CKE per rank.
M_SRFWEN
I
CMOS1.8
SUS
S3 Firewall Enable: DDR in self-refresh enable signal.
Should be connected to VCC180SR with an external pull-
up resistor.
M_CSB[1:0]
O
CMOS1.8
Core
Chip Select: These signals determine whether a
command is valid in a given cycle for the devices
connected to it. There is one M_CSB for each rank.
M_RASB
O
CMOS1.8
Core
Row Address Strobe: (active low) This signal is used
with M_CASB and M_WEB (along with M_CSB) to define
commands.
M_CASB
O
CMOS1.8
Core
Column Address Strobe: (active low) This signal is used
with M_RASB, M_WEB, and M_CSB to define commands.
M_WEB
O
CMOS1.8
Core
Write Enable: (active low) Used with M_CASB, M_RASB,
and M_CSB to define commands.
M_BS[2:0]
O
CMOS1.8
Core
Bank Select: (active high) Defines which banks are being
addressed within each rank. (Some call this Bank Address
(M_BA))
M_MA[14:0]
O
CMOS1.8
Core
Multiplexed Address: Provides multiplexed row and
column address to memory.
M_DQ[31:0]
I/O
CMOS1.8
Core Data Lines: M_DQ signals interface to the DRAM data bus
M_DQS[3:0]
I/O
CMOS1.8
Core
Data Strobes: These signals are used during writes,
driven by the processor, offset so as to be centered in the
data phase. During reads, these signals are driven by
memory devices edge aligned with data. The following list
matches the data strobe with the data bytes.
M_DQS[3] matches M_DQ[31:24]
M_DQS[2] matches M_DQ[23:16]
M_DQS[1] matches M_DQ[15:8]
M_DQS[0] matches M_DQ[7:0]
M_DM[3:0]
I/O
CMOS1.8
Core
Data Mask: One bit per byte indicating which bytes
should be written.
M_RCVENIN
I
CMOS1.8
Core
Receive Enable In: (active high) Connects to
M_RCVENOUT on the motherboard. This input enables the
M_DQS input buffers during reads.
M_RCVENOUT
O
CMOS1.8
Core
Receive Enable Out: (active high) Connects to
M_RCVENIN on the motherboard. Part of the feedback
used to enable the M_DQS input buffers during reads.
M_RCOMPOUT
I
A
Core
RCOMPOUT: Connected to a reference resistor to
dynamically calibrate the driver strengths.