Datasheet

Signal Description

Intel

Atom™ Processor E6xx Series Datasheet

2.0 Signal Description

This chapter provides a detailed description of the signals and boot strap definitions.

The processor signals are arranged in functional groups according to their associated

interface.

Each signal description table has the following headings:

• Signal: The name of the signal/pin

• Type: The buffer direction and type. Buffer direction can be either input, output, or

I/O (bidirectional). See Table 3 for definitions of the different buffer types.

• Power Well: The power plane used to supply power to that signal. Choices are

core, DDR, Suspend, and RTC.

• Description: A brief explanation of the signal’s function

Table 3. Buffer Types

Buffer Type Buffer Description

AGTL+

Assisted Gunning Transceiver Logic Plus. CMOS Open Drain interface signals that require

termination. Refer to the AGTL+ I/O Specification for complete details.

CMOS,

CMOS_OD

1.05-V CMOS buffer, or CMOS Open Drain

CMOS_HDA

CMOS buffers for Intel

HD Audio

interface that can be configured for either 1.5-V or 3.3-

V operation. The processor will only support 3.3-V

CMOS1.8

1.8-V CMOS buffer. These buffers can be configured as Stub Series Termination Logic

(SSTL1.8)

CMOS3.3,

CMOS3.3_OD

3.3-V CMOS buffer, or CMOS 3.3-V open drain

CMOS3.3-5 3.3-V CMOS buffer, 5-V tolerant

PCIe*

PCI Express* interface signals. These signals are compatible with PCI Express* Base

Specification, Rev. 1.0a Signaling Environment AC Specifications and are AC coupled. The

buffers are not 3.3-V tolerant.

SDVO

Serial-DVO differential buffers. These signals are AC coupled. These buffers are not 3.3-V

tolerant.

LVDS

Low Voltage Differential Signal output buffers. These pure outputs should drive across a

100-Ω resistor at the receiver when driving.

A Analog reference or output maybe used as a threshold voltage or for buffer compensation.