Datasheet

Introduction
Intel
®
Atom™ Processor E6xx Series Datasheet
28
1.3.4 Video Decode
The Intel
®
Atom™ Processor E6xx Series supports MPEG2, MPEG4, VC1, WMV9, H.264
(main, baseline at L3 and high-profile level 4.0/4.1), and DivX*.
1.3.5 Video Encode
The Intel
®
Atom™ Processor E6xx Series supports MPEG4, H.264 (baseline at L3), and
VGA.
1.3.6 Display Interfaces
The Intel
®
Atom™ Processor E6xx Series supports LVDS and Serial DVO display ports
permitting simultaneous independent operation of two displays.
1.3.6.1 LVDS Interface
The Intel
®
Atom™ Processor E6xx Series supports a Low-Voltage Differential Signaling
interface that allows the Graphics and Video adaptor to communicate directly to an on-
board flat-panel display. The LVDS interface supports pixel color depths of 18 and 24
bits, maximum resolution up to 1280x768 @ 60 Hz. Minimum pixel clock is 19.75 MHz.
Maximum pixel clock rate up to 80 MHz.
The processor does provides LVDS backlight control related signal in order to support
LVDS panel backlight adjustment.
1.3.6.2 Serial DVO (SDVO) Display Interface
Digital display channel capable of driving SDVO adapters that provide interfaces to a
variety of external display technologies (e.g., DVI, TV-Out, analog CRT). Maximum
resolution up to 1280x1024 @ 85 Hz. Maximum pixel clock rate up to 160 MHz.
SDVO lane reversal is not supported.
1.3.7 PCI Express*
The Intel
®
Atom™ Processor E6xx Series has four x1 lane PCI Express* (PCIe*) root
ports supporting the PCI Express* Base Specification, Rev. 1.0a. The processor does
not support the “ganging” of PCIe* ports. The four x1 PCIe* ports operate as four
independent PCIe* controllers. Each root port supports up to 2.5 Gb/s bandwidth in
each direction per lane.
The PCIe* ports may be used to attach discrete I/O components or a custom I/O Hub
for increased I/O expansion.
1.3.8 LPC Interface
The Intel
®
Atom™ Processor E6xx Series implements an LPC interface as described in
the LPC1.1 Specification.
The LPC interface has three PCI-based clock outputs that may be provided to different
I/O devices such as legacy I/O chip. The LPC_CLKOUT signals support a total of six
loads (two loads per clock pair) with no external buffering.