Datasheet

ACPI Devices
Intel
®
Atom™ Processor E6xx Series Datasheet
270
11.10.4 Theory Of Operation
11.10.4.1 RTC Well and WDT_TOUT Functionality
The WDT_TIMEOUT bit is set to a ‘1’ when the WDT 35-bit down counter reaches zero
for the second time in a row. Then the GPIO[4] pin is toggled HIGH by the WDT from
the processor. The board designer must attach the GPIO[4] to the appropriate external
signal. If WDT_TOUT_CNF is a ‘1’ the WDT toggles WDT_TOUT (GPIO[4]) again the
next time a time out occurs. Otherwise GPIO[4] is driven high until the system is reset
or power is cycled.
11.10.4.2 Register Unlocking Sequence
The register unlocking sequence is necessary whenever writing to the RELOAD register
or either PRELOAD_VALUE registers. The host must write a sequence of two writes to
offset WDTBA + 0Ch before attempting to write to either the WDT_RELOAD and
WDT_TIMEOUT bits of the RELOAD register or the PRELOAD_VALUE registers. The first
writes are “80” and “86” (in that order) to offset WDTBA + 0Ch. The next write is to the
proper memory mapped register (e.g., RELOAD, PRELOAD_VALUE_1,
PRELOAD_VALUE_2). Any deviation from the sequence (writes to memory-mapped
registers) causes the host to have to restart the sequence.
When performing register unlocking, software must issue the cycles using byte access
only. Otherwise the unlocking sequence will not work properly.
The following is an example of how to prevent a timeout:
1. Write “80” to offset WDTBA + 0Ch
2. Write “86” to offset WDTBA + 0Ch
3. Write a ‘1’ to RELOAD [8] (WDT_RELOAD) of the Reload Register
Note: Any subsequent writes require that this sequence be performed again.
01 0h RW WDT_ENABLE
Watchdog Timer Enable: The following bit enables or disables the WDT.
0 = Disabled (Default)
1 = Enabled
Note: This bit cannot be modified if WDT_LOCK has been set.
Note: In WDT mode Preload Value 1 is reloaded every time
WDT_ENABLE goes from ‘0’ to ‘1’ or the WDT_RELOAD bit is
written using the proper sequence of writes (See Register
Unlocking Sequence). When the WDT timeout occurs, a reset
must happen.
Note: Software must guarantee that a timeout is not about to occur
before disabling the timer. A reload sequence is suggested.
00 0h RWL WDT_LOCK
Watchdog Timer Lock: Setting this bit locks the values of this register
until a hard-reset occurs or power is cycled.
0 = Unlocked (Default)
1 = Locked
Note: Writing a “0” has no effect on this bit. Write is only allowed from
“0” to “1” once. It cannot be changed until either power is cycled
or a hard-reset occurs.
Table 400. 18h: WDTLR - WDT Lock Register (Sheet 2 of 2)
Size: 8 bit Default: 00h Power Well: Core
Access
PCI Configuration B:D:F
Offset Start:
Offset End:
18h
18h
IA F Base Address: Base (IO) Offset: 18h
Bit Range Default Access Acronym Description