Datasheet
ACPI Devices
Intel
®
Atom™ Processor E6xx Series Datasheet
269
11.10.3.11 Offset 15h: DCR1 - Down Counter Register 1
11.10.3.12 Offset 16h: DCR2 - Down Counter Register 2
11.10.3.13 Offset 18h: WDTLR - WDT Lock Register
Table 398. 15h: DCR1 - Down Counter Register 1
Size: 8 bit Default: 00h Power Well: Core
Access
PCI Configuration B:D:F
Offset Start:
Offset End:
15h
15h
IA F Base Address: Base (IO) Offset: 15h
Bit Range Default Access Acronym Description
07 : 00 00h RO DCNT_15_8
Down-Counter [15:8]: The Down-Counter register holds the bits 8
through 15 of upper 20-bits of the 35-bit down counter that is
continuously decremented. The values from Preload Registers are loaded
into the Down-Counter every time the WDT enters stage. The down
counter decrements using a 33 MHz clock.
Any reads to this register return an indeterminate value. This register is
to be indicated as reserved.
Table 399. 16h: DCR2 - Down Counter Register 2
Size: 8 bit Default: 00h Power Well: Core
Access
PCI Configuration B:D:F
Offset Start:
Offset End:
16h
16h
IA F Base Address: Base (IO) Offset: 16h
Bit Range Default Access Acronym Description
07 : 04 0h Reserved Reserved
03 : 00 0h RO DCNT_19_16
Down-Counter [19:16]: The Down-Counter register holds the bits 16
through 19 of upper 20-bits of the 35-bit down counter that is
continuously decremented. The values from Preload Registers are loaded
into the Down-Counter every time the WDT enters the stage. The down
counter decrements using a 33 MHz clock.
Note: Any reads to this register return an indeterminate value. This
register is to be indicated as reserved.
Table 400. 18h: WDTLR - WDT Lock Register (Sheet 1 of 2)
Size: 8 bit Default: 00h Power Well: Core
Access
PCI Configuration B:D:F
Offset Start:
Offset End:
18h
18h
IA F Base Address: Base (IO) Offset: 18h
Bit Range Default Access Acronym Description
07 : 03 0h Reserved Reserved
02 0h RW
WDT_TOUT_CN
F
WDT Timeout Configuration: This register is used to choose the
functionality of the timer.
Watchdog Timer Mode: When enabled (i.e. WDT_ENABLE goes from ‘0’ to
‘1’) the timer reloads Preload Value 1 and start decrementing. (Default)
Upon reaching timeout the GPIO[4] is driven high once and does not
change again until Power is cycled or a hard reset occurs.