Datasheet

ACPI Devices
Intel
®
Atom™ Processor E6xx Series Datasheet
268
11.10.3.9 Offset 10h: WDTCR - WDT Configuration Register
11.10.3.10 Offset 14h: DCR0 - Down Counter Register 0
Table 396. 10h: WDTCR - WDT Configuration Register
Size: 8 bit Default: 00h Power Well: Core
Access
PCI Configuration B:D:F
Offset Start:
Offset End:
10h
10h
IA F Base Address: Base (IO) Offset: 10h
Bit Range Default Access Acronym Description
07 : 06 00h RO Reserved Reserved
05 0h RW WDT_TOUT_EN
WDT Timeout Output Enable: This bit indicates whether or not the
WDT toggles the external GPIO[4] pin if the WDT times out.
0 = Enabled (Default)
1 = Disabled
04 0 RW
WDT_RESET_E
N
WDT Reset Enable: When this bit is enable (set to 1), it allows internal
reset to be trigger when WDT timeout. It either trigger COLD or WARM
reset depend on WDT_RESET_SEL bit.
0 = Disable internal reset (Default)
1 = Enable internal COLD or WARM reset.
03 0h RW
WDT_RESET_S
EL
WDT Reset Select: This determines which reset to be triggered when
WDT_RESET_EN is set.
0 = Cold Reset (Default)
1 = Warm Reset
02 0h RW WDT_PRE_SEL
WDT Prescaler Select: The WDT provides two options for prescaling the
main Down Counter. The preload values are loaded into the main down
counter right justified. The prescaler adjusts the starting point of the 35-
bit down counter.
0 = The 20-bit Preload Value is loaded into bits 34:15 of the main down
counter. The resulting timer clock is the PCI Clock (33 MHz) divided
by 2
15
. The approximate clock generated is 1 KHz, (1 ms to 10 min).
(Default)
1 = The 20-bit Preload Value is loaded into bits 24:05 of the main down
counter. The resulting timer clock is the PCI Clock (33 MHz) divided
by 2
5
. The approximate clock generated is 1 MHz, (1 µs to 1 sec)
01 : 00 00h RW RSVD Reserved
Table 397. 14h: DCR0 - Down Counter Register 0
Size: 8 bit Default: 00h Power Well: Core
Access
PCI Configuration B:D:F
Offset Start:
Offset End:
14h
14h
IA F Base Address: Base (IO) Offset: 14h
Bit Range Default Access Acronym Description
07 : 00 00h RO DCNT_7_0
Down-Counter [7:0]: The Down-Counter register holds the bits 0
through 7 of upper 20-bits of the 35-bit down counter that is
continuously decremented. The values from Preload Registers are loaded
into the Down-Counter every time the WDT enters stage. The down
counter decrements using a 33 MHz clock.
Any reads to this register return an indeterminate value. This register is
to be indicated as reserved.