Datasheet
ACPI Devices
Intel
®
Atom™ Processor E6xx Series Datasheet
267
11.10.3.7 Offset 0Ch: RR0 - Reload Register 0
11.10.3.8 Offset 0Dh: RR1 - Reload Register 1
03 : 00 Fh RW PLOAD2_19_16
Preload_Value_2 [19:16]: This register is used to hold the bits 16
through 19 of the preload value 2 for the WDT Timer. The Value in the
Preload Register is automatically transferred into the 35-bit down
counter.
The value loaded into the preload register needs to be one less than the
intended period. This is because the timer makes use of zero-based
counting (i.e. zero is counted as part of the decrement).
Refer to Section 11.10.4.2 for details on how to change the value of this
register.
Table 394. 0Ch: RR0 - Reload Register 0
Size: 8 bit Default: 00h Power Well: Core
Access
PCI Configuration B:D:F
Offset Start:
Offset End:
0Ch
0Ch
IA F Base Address: Base (IO) Offset: 0Ch
Bit Range Default Access Acronym Description
07 : 00 00h Reserved Reserved. Must be programmed to 0.
Table 395. 0Dh: RR1 - Reload Register 1
Size: 8 bit Default: 00h Power Well: Core
Access
PCI Configuration B:D:F
Offset Start:
Offset End:
0Dh
0Dh
IA F Base Address: Base (IO) Offset: 0Dh
Bit Range Default Access Acronym Description
07 : 02 00h Reserved Reserved
01 0h RWC TOUT
WDT_TIMEOUT: This bit is located in the RTC Well and it’s value is not
lost if the host resets the system. It is set to ‘1’ if the host fails to reset
the WDT before the 35-bit Down-Counter reaches zero for the second
time in a row. This bit is cleared by performing the Register Unlocking
Sequence followed by a ‘1’ to this bit.
0 = Normal (Default)
1 = System has become unstable.
00 0h RW RELOAD
WDT_RELOAD: To prevent a timeout the host must perform the
Register Unlocking Sequence followed by a ‘1’ to this bit.
Refer to Section 11.10.4.2 for details on how to change the value of this
register.
Table 393. 06h: PV2R2 - Preload Value 2 Register 2 (Sheet 2 of 2)
Size: 8 bit Default: 0Fh Power Well: Core
Access
PCI Configuration B:D:F
Offset Start:
Offset End:
06h
06h
IA F Base Address: Base (IO) Offset: 06h
Bit Range Default Access Acronym Description