Datasheet
ACPI Devices
Intel
®
Atom™ Processor E6xx Series Datasheet
266
11.10.3.4 Offset 04h: PV2R0 - Preload Value 2 Register 0
11.10.3.5 Offset 05h: PV2R1 - Preload Value 2 Register 1
11.10.3.6 Offset 06h: PV2R2 - Preload Value 2 Register 2
Table 391. 04h: PV2R0 - Preload Value 2 Register 0
Size: 8 bit Default: FFh Power Well: Core
Access
PCI Configuration B:D:F
Offset Start:
Offset End:
04h
04h
IA F Base Address: Base (IO) Offset: 04h
Bit Range Default Access Acronym Description
07 : 00 FFh RW PLOAD2_7_0
Preload_Value_2 [7:0]: This register is used to hold the bits 0 through
7 of the preload value 2 for the WDT Timer. The Value in the Preload
Register is automatically transferred into the 35-bit down counter.
The value loaded into the preload register needs to be one less than the
intended period. This is because the timer makes use of zero-based
counting (i.e., zero is counted as part of the decrement).
Refer to Section 11.10.4.2 for details on how to change the value of this
register.
Table 392. 05h: PV2R1 - Preload Value 2 Register 1
Size: 8 bit Default: FFh Power Well: Core
Access
PCI Configuration B:D:F
Offset Start:
Offset End:
05h
05h
IA F Base Address: Base (IO) Offset: 05h
Bit Range Default Access Acronym Description
07 : 00 FFh RW PLOAD2_15_8
Preload_Value_2 [15:8]: This register is used to hold the bits 8
through 15 of the preload value 2 for the WDT Timer. The Value in the
Preload Register is automatically transferred into the 35-bit down
counter.
The value loaded into the preload register needs to be one less than the
intended period. This is because the timer makes use of zero-based
counting (i.e., zero is counted as part of the decrement).
Refer to Section 11.10.4.2 for details on how to change the value of this
register.
Table 393. 06h: PV2R2 - Preload Value 2 Register 2 (Sheet 1 of 2)
Size: 8 bit Default: 0Fh Power Well: Core
Access
PCI Configuration B:D:F
Offset Start:
Offset End:
06h
06h
IA F Base Address: Base (IO) Offset: 06h
Bit Range Default Access Acronym Description
07 : 04 0h Reserved Reserved