Datasheet

ACPI Devices
Intel
®
Atom™ Processor E6xx Series Datasheet
265
11.10.3.2 Offset 01h: PV1R1 - Preload Value 1 Register 1
11.10.3.3 Offset 02h: PV1R2 - Preload Value 1 Register 2
Table 389. 01h: PV1R1 - Preload Value 1 Register 1
Size: 8 bit Default: FFh Power Well: Core
Access
PCI Configuration B:D:F
Offset Start:
Offset End:
01h
01h
IA F Base Address: Base (IO) Offset: 01h
Bit Range Default Access Acronym Description
07 : 00 FFh RW PLOAD1_15_8
Preload_Value_1 [15:8]: This register is used to hold the bits 8
through 15 of the preload value 1 for the WDT Timer. The Value in the
Preload Register is automatically transferred into the 35-bit down
counter.
The value loaded into the preload register needs to be one less than the
intended period. This is because the timer makes use of zero-based
counting (i.e. zero is counted as part of the decrement).
Refer to Section 11.10.4.2 for details on how to change the value of this
register.
Table 390. 02h: PV1R2 - Preload Value 1 Register 2
Size: 8 bit Default: FFh Power Well: Core
Access
PCI Configuration B:D:F
Offset Start:
Offset End:
02h
02h
IA F Base Address: Base (IO) Offset: 02h
Bit Range Default Access Acronym Description
07 : 04 0h Reserved Reserved
03 : 00 Fh RW PLOAD_19_16
Preload_Value_1 [19:16]: This register is used to hold the bits 16
through 19 of the preload value 1 for the WDT Timer. The Value in the
Preload Register is automatically transferred into the 35-bit down
counter.
The value loaded into the preload register needs to be one less than the
intended period. This is because the timer makes use of zero-based
counting (i.e. zero is counted as part of the decrement).
Refer to Section 11.10.4.2 for details on how to change the value of this
register.